J. Bonnano, A. Collura, D. Lipetz, U. Mayer, B. Prasky et al., Two level bulk preload branch prediction, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 2013.
DOI : 10.1109/HPCA.2013.6522308

P. Chang, M. Evers, and Y. N. Patt, Improving branch prediction accuracy by reducing pattern history table interference, International Conference on Parallel Architectures and Compilation Techniques (PACT), 1996.
DOI : 10.1007/BF02699882

URL : http://www.eecs.umich.edu/HPS/pub/filter_pact96.ps

P. Chang, E. Hao, and Y. N. Patt, Target prediction for indirect jumps, International Symposium on Computer Architecture (ISCA), 1997.
DOI : 10.1145/264107.264209

URL : http://www.eecs.umich.edu/HPS/pub/indir_isca24.ps

P. Chang, E. Hao, T. Yeh, and Y. Patt, Branch classification, Proceedings of the 27th annual international symposium on Microarchitecture , MICRO 27, 1994.
DOI : 10.1145/192724.192727

P. Chang, E. Hao, T. Yeh, and Y. N. Patt, Alternative implementations of hybrid branch predictors, International Symposium on Microarchitecture (MICRO), 1995.

I. Chen, Enhancing the instruction fetching mechanism using data compresssion, 1997.

I. K. Chen, J. T. Coffey, and T. N. Mudge, Analysis of branch prediction via data compression, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 1996.
DOI : 10.1145/237090.237171

URL : http://cardit.et.tudelft.nl/~heco/lit/chen96.ps.gz

J. G. Cleary and I. H. Witten, Data Compression Using Adaptive Coding and Partial String Matching, IEEE Transactions on Communications, vol.32, issue.4, 1984.
DOI : 10.1109/TCOM.1984.1096090

URL : http://cs.haifa.ac.il/courses/src_coding/ClearyWitten1984BasicPPM.pdf

K. Driesen and U. Hölzle, Accurate indirect branch prediction, International Symposium on Computer Architecture (ISCA), 1998.
DOI : 10.1109/isca.1998.694772

URL : http://web.archive.org/web/19990221111215/www.cs.ucsb.edu/oocsb/papers/TRCS97-19.pdf

K. Driesen and U. Hölzle, The cascaded predictor: economical and adaptive branch target prediction, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture, 1998.
DOI : 10.1109/MICRO.1998.742786

URL : http://www.cs.ucsb.edu/TRs/Docs/TRCS98-17.ps

K. Driesen and U. Hölzle, Multi-stage Cascaded Prediction, International Euro-Par Conference on Parallel Processing, 1999.
DOI : 10.1007/3-540-48311-X_186

URL : http://www.cs.ucsb.edu/TRs/Docs/TRCS99-05.ps

A. N. Eden and T. Mudge, The YAGS branch prediction scheme, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture, 1998.
DOI : 10.1109/MICRO.1998.742770

URL : http://www.cs.berkeley.edu/~kubitron/courses/cs252-F99/handouts/papers/mudge_yags.pdf

M. Evers, Improving branch prediction by understanding branch behavior, 2000.

M. Evers, P. Chang, and Y. N. Patt, Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches, International Symposium on Computer Architecture (ISCA), 1996.

E. Federovsky, M. Feder, and S. Weiss, Branch prediction based on universal data compression algorithms, International Symposium on Computer Architecture (ISCA), 1998.
DOI : 10.1109/isca.1998.694763

H. Gao and H. Zhou, Adaptive information processing: an effective way to improve perceptron predictors, Journal of Instruction-Level Parallelism, vol.7, 2004.

H. Gao and H. Zhou, PMPM: prediction by combining multiple partial matches, Journal of Instruction-Level Parallelism, vol.9, 2006.

D. Gope and M. H. Lipasti, Bias-Free Branch Predictor, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014.
DOI : 10.1109/MICRO.2014.32

D. Gope and M. H. Lipasti, Bias-free neural predictor, Championship Branch Prediction (CBP-4), 2014.
DOI : 10.1109/micro.2014.32

R. N. Ibbett, The MU5 Instruction Pipeline, The Computer Journal, vol.15, issue.1, 1972.
DOI : 10.1093/comjnl/15.1.42

URL : https://academic.oup.com/comjnl/article-pdf/15/1/42/1160478/15-1-42.pdf

Y. Ishii, Fused two-level branch prediction with ahead calculation, Journal of Instruction-Level Parallelism, vol.9, 2006.

Y. Ishii, K. Kuroyanagi, T. Sawada, M. Inaba, and K. Hiraki, Revisiting local history for improving fused twolevel branch prediction, Championship Branch Prediction (CBP-3), 2011.

D. Jiménez, Multiperspective perceptron predictor, Championship Branch Prediction, 2016.

D. Jiménez, Multiperspective perceptron predictor with TAGE, Championship Branch Prediction (CBP-5), 2016.

D. A. Jiménez, Fast path-based neural branch prediction, 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449), 2003.
DOI : 10.1109/MICRO.2003.1253199

D. A. Jiménez, Piecewise linear branch prediction, International Symposium on Computer Architecture (ISCA), 2005.

D. A. Jiménez, OH-SNAP: optimized hybrid scaled neural analog predictor, Championship Branch Prediction (CBP-3), 2011.

D. A. Jiménez, Strided sampling hashed perceptron predictor, Championship Branch Prediction (CBP-4), 2014.

D. A. Jiménez and C. Lin, Dynamic branch prediction with perceptrons, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, 2001.
DOI : 10.1109/HPCA.2001.903263

D. A. Jiménez and C. Lin, Composite Confidence Estimators for Enhanced Speculation Control, 2009 21st International Symposium on Computer Architecture and High Performance Computing, 2002.
DOI : 10.1109/SBAC-PAD.2009.17

D. A. Jiménez and C. Lin, Neural methods for dynamic branch prediction, ACM Transactions on Computer Systems, vol.20, issue.4, 2002.
DOI : 10.1145/571637.571639

J. Kalamatianos and D. R. Kaeli, Predicting indirect branches via data compression, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture, 1998.
DOI : 10.1109/MICRO.1998.742789

URL : http://www.ece.neu.edu/info/architecture/publications/micro98.ps.gz

C. Lee, I. K. Chen, and T. N. Mudge, The bi-mode branch predictor, International Symposium on Microarchitecture (MICRO), 1997.

J. K. Lee and A. J. Smith, Branch Prediction Strategies and Branch Target Buffer Design, Computer, vol.17, issue.1, 1984.
DOI : 10.1109/MC.1984.1658927

G. H. Loh and D. S. Henry, Predicting conditional branches with fusion-based hybrid predictors, Proceedings.International Conference on Parallel Architectures and Compilation Techniques, 2002.
DOI : 10.1109/PACT.2002.1106015

S. Mcfarling, Combining branch predictors, 1993.

S. Mcfarling, Branch predictor with serially connected predictor stages for improving branch prediction accuracy . US patent 6374349, 1998.

S. Mcfarling, S. C. Steely-jr, J. Emer, and E. Mclellan, Trainable apparatus for predicting instruction outcomes in pipelined processors, 1994.

P. Michaud, A PPM-like, tag-based predictor, Journal of Instruction-Level Parallelism, vol.7, 2004.

P. Michaud and A. Seznec, A comprehensive study of dynamic global history branch prediction, 2001.
URL : https://hal.archives-ouvertes.fr/inria-00072400

P. Michaud, A. Seznec, and R. Uhlig, Trading conflict and capacity aliasing in conditional branch predictors, International Symposium on Computer Architecture (ISCA), 1997.
DOI : 10.1145/264107.264211

R. Nair, Dynamic path-based branch correlation, Proceedings of the 28th Annual International Symposium on Microarchitecture, 1995.
DOI : 10.1109/MICRO.1995.476809

R. Nair, Optimal 2-bit branch predictors, IEEE Transactions on Computers, vol.44, issue.5, 1995.
DOI : 10.1109/12.381956

S. Pan, K. So, and J. T. Rameh, Improving the accuracy of dynamic branch prediction using branch correlation, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 1992.
DOI : 10.1145/143365.143490

C. G. Ponder and M. C. Shebanow, An information-theoretic look at branch-prediction Studies in branchprediction, 1990.
DOI : 10.2172/6569918

URL : https://www.osti.gov/servlets/purl/6569918

D. J. Schlais and M. H. Lipasti, BADGR: A practical GHR implementation for TAGE branch predictors, 2016 IEEE 34th International Conference on Computer Design (ICCD), 2016.
DOI : 10.1109/ICCD.2016.7753338

S. Sechrest, C. Lee, and T. Mudge, Correlation and aliasing in dynamic branch predictors, International Symposium on Computer Architecture (ISCA), 1996.
DOI : 10.1145/232973.232978

A. Seznec, https://team.inria.fr/pacap/members/andre-seznec

A. Seznec, An optimized 2bcgskew branch predictor. https://team.inria, 2003.

A. Seznec, Redundant history skewed perceptron predictors: pushing limits on global history branch predictors, 2003.

A. Seznec, The O-GEHL branch predictor, Championship Branch Prediction (CBP-1), 2004.

A. Seznec, Revisiting the perceptron predictor, 2004.

A. Seznec, Analysis of the O-geometric history length branch predictor, International Symposium on Computer Architecture (ISCA), 2005.
DOI : 10.1145/1080695.1070003

URL : http://courses.engr.illinois.edu/ece512/Papers/Seznec.2005.ISCA.pdf

A. Seznec, The idealistic GTL predictor, Journal of Instruction-Level Parallelism, vol.9, 2006.

A. Seznec, The L-TAGE branch predictor, Journal of Instruction-Level Parallelism, vol.9, 2006.

A. Seznec, A 64 Kbytes ISL-TAGE branch predictor, Championship Branch Prediction (CBP-3), 2011.
DOI : 10.1145/2155620.2155635

URL : https://hal.archives-ouvertes.fr/hal-00639040

A. Seznec, A new case for the TAGE branch predictor, Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-44 '11, 2011.
DOI : 10.1145/2155620.2155635

URL : https://hal.archives-ouvertes.fr/hal-00639193

A. Seznec, Storage free confidence estimation for the TAGE branch predictor, 2011 IEEE 17th International Symposium on High Performance Computer Architecture, 2011.
DOI : 10.1109/HPCA.2011.5749750

URL : https://hal.archives-ouvertes.fr/inria-00512130

A. Seznec, TAGE-SC-L branch predictors again, Championship Branch Prediction (CBP-5), 2016.
URL : https://hal.archives-ouvertes.fr/hal-01354253

A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides, Design tradeoffs for the Alpha EV8 conditional branch predictor, International Symposium on Computer Architecture (ISCA), 2002.
DOI : 10.1109/isca.2002.1003587

URL : http://courses.ece.uiuc.edu/ece512/papers/seznec.2002.isca.pdf

A. Seznec and P. Michaud, De-aliased hybrid branch predictors, 1999.
URL : https://hal.archives-ouvertes.fr/inria-00073060

A. Seznec and P. Michaud, A case for (partially) tagged geometric history length branch prediction, Journal of Instruction-Level Parallelism, vol.8, 2006.

J. E. Smith, A study of branch prediction strategies, 25 years of the international symposia on Computer architecture (selected papers) , ISCA '98, 1981.
DOI : 10.1145/285930.285980

URL : http://clue.eng.iastate.edu/~zzhang/courses/cpre585-f03/reading/smith-isca81-bpred.pdf

M. K. Smotherman, E. H. Sussenguth, and R. J. Robelen, The IBM ACS project, IEEE Annals of the History of Computing, vol.38, issue.1, 2016.
DOI : 10.1109/mahc.2015.50

E. Sprangle, R. S. Chappell, M. Alsup, and Y. N. Patt, The agree predictor: a mechanism for reducing negative branch history interference, International Symposium on Computer Architecture (ISCA), 1997.

R. St, D. A. Amant, D. Jiménez, and . Burger, Low-power, high-performance analog neural branch prediction, International Symposium on Microarchitecture (MICRO), 2008.

A. R. Talcott, M. Nemirovsky, and R. C. Wood, The influence of branch prediction table interference on branch prediction scheme performance, International Conference on Parallel Architectures and Compilation Techniques (PACT), 1995.
DOI : 10.1109/isca.1994.288165

D. Tarjan and K. Skadron, Revisiting the perceptron predictor again, 2004.

D. Tarjan and K. Skadron, Merging path and gshare indexing in perceptron branch prediction, ACM Transactions on Architecture and Code Optimization, vol.2, issue.3, 2005.
DOI : 10.1145/1089008.1089011

URL : http://www.cs.virginia.edu/~dtarjan/Papers/CS-2004-38.pdf

L. N. Vintan and M. Iridon, Towards a high performance neural branch predictor, IJCNN'99. International Joint Conference on Neural Networks. Proceedings (Cat. No.99CH36339), 1999.
DOI : 10.1109/IJCNN.1999.831066

URL : http://webspace.ulbsibiu.ro/lucian.vintan/html/USA.pdf

T. Yeh and Y. N. Patt, Two-level adaptive training branch prediction, Proceedings of the 24th annual international symposium on Microarchitecture , MICRO 24, 1991.
DOI : 10.1145/123465.123475

T. Yeh and Y. N. Patt, Alternative implementations of two-level adaptive branch prediction, International Symposium on Computer Architecture (ISCA), 1992.

T. Yeh and Y. N. Patt, A comparison of dynamic branch predictors that use two levels of branch history, International Symposium on Computer Architecture (ISCA), 1993.

C. Young, N. Gloy, and M. D. Smith, A comparative analysis of schemes for correlated branch prediction, International Symposium on Computer Architecture (ISCA), 1995.
DOI : 10.1109/isca.1995.524568

URL : https://dash.harvard.edu/bitstream/handle/1/24015805/tr-06-95.pdf?sequence=3

C. Zhang, Mars: a 64-core ARMv8 processor. Hot Chips, 2015.
DOI : 10.1109/hotchips.2015.7477454