Software pipelining, ACM Computing Surveys, vol.27, issue.3, 1995. ,
Scheduling for embedded real-time systems, IEEE Design & Test of Computers, vol.15, issue.1, pp.71-82, 1998. ,
DOI : 10.1109/54.655185
Multiprocessor Scheduling for Real-Time Systems, 2015. ,
DOI : 10.1007/978-3-319-08696-5
Rigorous Component-Based System Design Using the BIP Framework, IEEE Software, vol.28, issue.3, 2011. ,
DOI : 10.1109/MS.2011.27
URL : https://hal.archives-ouvertes.fr/hal-00722395
The C11 and C++11 Concurrency Model, 2014. ,
Clock-directed modular code generation for synchronous data-flow languages, Proceedings LCTES, 2008. ,
DOI : 10.1145/1379023.1375674
Static Mapping of Real-Time Applications onto Massively Parallel Processor Arrays, 2014 14th International Conference on Application of Concurrency to System Design, 2014. ,
DOI : 10.1109/ACSD.2014.19
URL : https://hal.archives-ouvertes.fr/hal-01095130
Predicate-aware, makespan-preserving software pipelining of scheduling tables, ACM Transactions on Architecture and Code Optimization, vol.11, issue.1, 2014. ,
DOI : 10.1109/ICPP.2002.1040919
URL : https://hal.archives-ouvertes.fr/hal-01095123
From dataflow specification to multiprocessor partitioned time-triggered real-time implementation, Leibniz Transactions on Embedded Systems, vol.2, issue.2, p.2015 ,
URL : https://hal.archives-ouvertes.fr/hal-00742908
From simulink to scade/lustre to tta: A layered approach for distributed embedded applications, Proceedings LCTES, 2003. ,
DOI : 10.1145/780732.780754
Lustre: A declarative language for programming synchronous systems, POPL, 1987. ,
DOI : 10.1145/41625.41641
Combined task-and network-level scheduling for distributed time-triggered networked systems, Real-Time Systems, vol.52, issue.2, p.2016 ,
DOI : 10.1007/s11241-015-9244-x
Efficiently computing static single assignment form and the control dependence graph, ACM Transactions on Programming Languages and Systems, vol.13, issue.4, pp.451-490, 1991. ,
DOI : 10.1145/115372.115320
URL : http://grothoff.org/christian/teaching/2007/3353/papers/ssa.pdf
On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling, Formal Modeling and Analysis of Timed Systems (FORMATS2015), 2015. ,
DOI : 10.1007/978-3-319-22975-1_8
URL : https://hal.archives-ouvertes.fr/hal-01179489
Critical path profiling of message passing and shared-memory programs, IEEE Transactions on Parallel and Distributed Systems, vol.9, issue.10, pp.1029-1040, 1998. ,
DOI : 10.1109/71.730530
URL : http://www.cs.umd.edu/~hollings/papers/tpds98.pdf
Accessed 20 Instruction scheduling for superscalar and vliw platforms. temporal perspective. https://llvm.org/devmtg, 2012. ,
A comparative study of multiprocessor list scheduling heuristics, Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences HICSS-94, pp.68-77, 1994. ,
DOI : 10.1109/HICSS.1994.323184
The OASIS Kernel: A Framework for High Dependability Real-Time Systems, 2011 IEEE 13th International Symposium on High-Assurance Systems Engineering, 2011. ,
DOI : 10.1109/HASE.2011.38
MARTE: A Profile for RT/E Systems Modeling, Analysis - and Simulation?, Proceedings of the First International ICST Conference on Simulation Tools and Techniques for Communications Networks and Systems, 2008. ,
DOI : 10.4108/ICST.SIMUTOOLS2008.3097
URL : https://hal.archives-ouvertes.fr/inria-00371397
Advanced Compiler Design and Implementation, 1997. ,
Automatic wcet analysis of real-time parallel applications, Proceedings of the 3rd Workshop on Worst-Case Execution Time Analysis (WCET 2013), 2013. ,
URL : https://hal.archives-ouvertes.fr/hal-01239727
A model based safety critical flow for the aurix?multi-core platform, Proceedings ERTS2, 2018. ,
Mapping hard realtime applications on many-core processors, Real-Time Networks and Systems (RTNS2016), 2016. ,
DOI : 10.1145/2997465.2997496
URL : https://hal.archives-ouvertes.fr/hal-01692702
Clock-driven distributed real-time implementation of endochronous synchronous programs, Proceedings of the seventh ACM international conference on Embedded software, EMSOFT '09, 2009. ,
DOI : 10.1145/1629335.1629356
URL : https://hal.archives-ouvertes.fr/inria-00485007
Integrated worst-case execution time estimation of multicore applications, Proceedings of the WCET workshop, 2013. ,
URL : https://hal.archives-ouvertes.fr/hal-00909330
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing, Proceedings of the 14th annual workshop on Microprogramming, 1981. ,
DOI : 10.1145/1014192.802449
URL : http://www.ece.iupui.edu/~johnlee/ECE565/papers/p183-rau.pdf
Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor, Proceedings of the 24th International Conference on Real-Time Networks and Systems, RTNS '16, 2016. ,
DOI : 10.1109/RTAS.2016.7461361
URL : https://hal.archives-ouvertes.fr/hal-01406145
Defining and translating a "safe" subset of simulink/stateflow into lustre, Proceedings of the fourth ACM international conference on Embedded software , EMSOFT '04, 2004. ,
DOI : 10.1145/1017753.1017795
URL : http://www-verimag.imag.fr/TR/TR-2004-16.pdf
Efficient DAG construction and heuristic calculation for instruction scheduling, Proceedings of the 24th annual international symposium on Microarchitecture , MICRO 24, 1991. ,
DOI : 10.1145/123465.123482
A bridging model for parallel computation, Communications of the ACM, vol.33, issue.8, 1990. ,
DOI : 10.1145/79173.79181
The worst-case execution-time problem???overview of methods and survey of tools, ACM Transactions on Embedded Computing Systems, vol.7, issue.3, pp.1-36, 2008. ,
DOI : 10.1145/1347375.1347389
Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.28, issue.7, p.28, 2009. ,
DOI : 10.1109/TCAD.2009.2013287