Skip to Main content Skip to Navigation
New interface
Conference papers

Boosting Transactional Memory with Stricter Serializability

Abstract : Transactional memory (TM) guarantees that a sequence of operations encapsulated into a transaction is atomic. This simple yet powerful paradigm is a promising direction for writing concurrent applications. Recent TM designs employ a time-based mechanism to leverage the performance advantage of invisible reads. With the advent of many-core architectures and non-uniform memory (NUMA) architectures, this technique is however hitting the synchronization wall of the cache coherency protocol. To address this limitation, we propose a novel and flexible approach based on a new consistency criteria named stricter serializability ($${\text {SSER}^+}$$SSER+). Workloads executed under $${\text {SSER}^+}$$SSER+ are opaque when the object graph forms a tree and transactions traverse it top-down. We present a matching algorithm that supports invisible reads, lazy snapshots, and that can trade synchronization for more parallelism. Several empirical results against a well-established TM design demonstrate the benefits of our solution
Complete list of metadata

Cited literature [34 references]  Display  Hide  Download
Contributor : Hal Ifip Connect in order to contact the contributor
Submitted on : Friday, June 22, 2018 - 2:56:08 PM
Last modification on : Monday, August 24, 2020 - 4:16:13 PM
Long-term archiving on: : Monday, September 24, 2018 - 2:20:51 PM


Files produced by the author(s)


Distributed under a Creative Commons Attribution 4.0 International License



Pierre Sutra, Patrick Marlier, Valerio Schiavoni, François Trahay. Boosting Transactional Memory with Stricter Serializability. 20th International Conference on Coordination Languages and Models (COORDINATION), Jun 2018, Madrid, Spain. pp.231-251, ⟨10.1007/978-3-319-92408-3_11⟩. ⟨hal-01821500⟩



Record views


Files downloads