Controllable QoS for Imprecise Computation Tasks on DVFS Multicores with Time and Energy Constraints - Inria - Institut national de recherche en sciences et technologies du numérique Accéder directement au contenu
Article Dans Une Revue IEEE Journal on Emerging and Selected Topics in Circuits and Systems Année : 2018

Controllable QoS for Imprecise Computation Tasks on DVFS Multicores with Time and Energy Constraints

Résumé

Multicore architectures have been used to enhance computing capabilities, but the energy consumption is still an important concern. Embedded application domains usually require less accurate, but always in-time, results. Imprecise Computation (IC) can be used to divide a task into a mandatory subtask providing a baseline QoS and an optional subtask that further increases the baseline QoS. This work aims at maximizing the system QoS by solving task mapping and DVFS for dependent IC-tasks under real-time and energy constraints. Compared with existing approaches, we consider the joint-design problem, where task-to-processor allocation, frequency-to-task assignment, task scheduling and task adjustment are optimized simultaneously. The joint-design problem is formulated as an N P-hard Mixed-Integer Non-Linear Programming and it is safely transformed to a Mixed-Integer Linear Programming (MILP) without performance degradation. Two methods (basic and accelerated version) are proposed to find the optimal solution to MILP problem. They are based on problem decomposition and provide a controllable way to trade-off the quality of the solution and the computational complexity. The optimality of the proposed methods is proved rigorously, and the experimental results show reduced computation time (23.7% in average) compared with existing optimal methods.
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Dates et versions

hal-01831297 , version 1 (05-07-2018)

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Lei Mo, Angeliki Kritikakou, Olivier Sentieys. Controllable QoS for Imprecise Computation Tasks on DVFS Multicores with Time and Energy Constraints. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2018, 8 (4), pp.708-721. ⟨10.1109/JETCAS.2018.2852005⟩. ⟨hal-01831297⟩
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