Skip to Main content Skip to Navigation
Conference papers

Low Latency FPGA Implementation of Izhikevich-Neuron Model

Abstract : The Izhikevich’s simple model (ISM) for neural activity presents a good compromise between waveform quality and computational cost. FPGAs (Field Programmable Gate Array) are powerful, flexible, and inexpensive digital hardware that can implement such model. In this paper, we present a highly combinational, low latency implementation of ISM for FPGA. In the absence of official benchmark to compare different implementations, we propose two different metrics to compare the technical literature with our implementation. In this benchmark, we can implement a system that, when compared to the literature, has almost 1.5 times the number of digital neurons (DN), and latency more than 56 times smaller. This shows that our implementation is best suited for hybrid network systems and presents a fair performance for only-artificial networks.
Document type :
Conference papers
Complete list of metadata

Cited literature [12 references]  Display  Hide  Download
Contributor : Hal Ifip Connect in order to contact the contributor
Submitted on : Monday, August 6, 2018 - 3:10:17 PM
Last modification on : Friday, January 7, 2022 - 11:00:13 AM
Long-term archiving on: : Wednesday, November 7, 2018 - 2:11:36 PM


Files produced by the author(s)


Distributed under a Creative Commons Attribution 4.0 International License



Vitor Bandeira, Vivianne L. Costa, Guilherme Bontorin, Ricardo Reis. Low Latency FPGA Implementation of Izhikevich-Neuron Model. 5th International Embedded Systems Symposium (IESS), Nov 2015, Foz do Iguaçu, Brazil. pp.210-217, ⟨10.1007/978-3-319-90023-0_17⟩. ⟨hal-01854162⟩



Record views


Files downloads