M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik et al., Addressing the System-on-a-chip Interconnect Woes Through Communicationbased Design, Design Automation Conference (DAC). ACM, pp.667-672, 2001.

J. Owens, W. Dally, R. Ho, D. N. Jayasimha, S. Keckler et al., Research Challenges for On-Chip Interconnection Networks, IEEE Micro, vol.27, issue.5, pp.96-108, 2007.
DOI : 10.1109/MM.2007.4378787

W. Dally and B. Towles, Route packets, not wires: on-chip interconnection networks, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232), pp.684-689, 2001.
DOI : 10.1109/DAC.2001.935594

F. Moraes, N. Calazans, A. Mello, L. Möller, and L. Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, vol.38, issue.1, pp.69-93, 2004.
DOI : 10.1016/j.vlsi.2004.03.003

S. Foroutan, Y. Thonnart, R. Hersemeule, and A. Jerraya, An analytical method for evaluating Network-on-Chip performance, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp.1629-1632, 2010.
DOI : 10.1109/DATE.2010.5457072

G. Schirner and R. Dömer, ABSTRACT COMMUNICATION MODELING, From Specification to Embedded Systems Application, 2005.
DOI : 10.1007/11523277_19

, Quantitative Analysis of Transaction Level Models for the AMBA Bus, Design, Automation and Test in Europe (DATE), pp.1-6, 2006.

K. Lu, D. Muller-gritschneder, and U. Schlichtmann, Accurately timed transaction level models for virtual prototyping at high abstraction level, Design, Automation Test in Europe Conference Exhibition (DATE), pp.135-140, 2012.

L. Indrusiak and O. Santos, Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration, 2011 Design, Automation & Test in Europe, pp.1-6, 2011.
DOI : 10.1109/DATE.2011.5763179

A. Nayebi, S. Meraji, A. Shamaei, and H. Sarbazi-azad, XMulator: A Listener-Based Integrated Simulation Platform for Interconnection Networks, First Asia International Conference on Modelling & Simulation (AMS'07), pp.128-132, 2007.
DOI : 10.1109/AMS.2007.112

N. Jiang, D. Becker, G. Michelogiannakis, J. Balfour, B. Towles et al., A detailed and flexible cycle-accurate Network-on-Chip simulator, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp.86-96, 2013.
DOI : 10.1109/ISPASS.2013.6557149

URL : http://crd.lbl.gov/assets/booksimispass.pdf

M. Hosseinabady and J. Nunez-yanez, SystemC architectural transaction level modelling for large NoCs, 2010 Forum on Specification & Design Languages (FDL 2010), pp.1-6, 2010.
DOI : 10.1049/ic.2010.0143

E. Viaud, D. Potop-butucaru, and A. Greiner, An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles, Proceedings of the Design Automation & Test in Europe Conference, pp.1-6, 2006.
DOI : 10.1109/DATE.2006.244003

URL : https://hal.archives-ouvertes.fr/hal-01338224

S. Suboh, M. Bakhouya, J. Gaber, and T. El-ghazawi, Analytical modeling and evaluation of network-on-chip architectures, 2010 International Conference on High Performance Computing & Simulation, pp.615-622, 2010.
DOI : 10.1109/HPCS.2010.5547064

U. Ogras, P. Bogdan, and R. Marculescu, An Analytical Approach for Network-on-Chip Performance Analysis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, issue.12, pp.2001-2013, 2010.
DOI : 10.1109/TCAD.2010.2061613

H. Van-moll, H. Corporaal, V. Reyes, and M. Boonen, Fast and accurate protocol specific bus modeling using TLM 2.0, " in Design, Automation Test in Europe, pp.316-319, 2009.

F. Ghenassia, Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems, 2006.
DOI : 10.1007/b137175

A. Gerstlauer, R. Dömer, J. Peng, and D. D. Gajski, System Design: A Practical Guide with SpecC, 2001.
DOI : 10.1007/978-1-4615-1481-7

M. L. Fulgham and L. Snyder, Performance of Chaos and Oblivious Routers Under Nonuniform Traffic, Tech. Rep, 1993.

A. Mello, L. Tedesco, N. Calazans, and F. Moraes, Virtual channels in networks on chip, Proceedings of the 18th annual symposium on Integrated circuits and system design , SBCCI '05, pp.178-183, 2005.
DOI : 10.1145/1081081.1081128