Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance

Matthias Függer 1, 2, 3, 4 Attila Kinali 5, 6 Christoph Lenzen 5, 6 Ben Wiederhake 5, 6
1 CNRS - Centre National de la Recherche Scientifique
2 LSV - Laboratoire Spécification et Vérification [Cachan]
3 ENS Paris Saclay - Ecole Normale Supérieure Paris-Saclay
4 MEXICO - Modeling and Exploitation of Interaction and Concurrency
LSV - Laboratoire Spécification et Vérification [Cachan], ENS Cachan - École normale supérieure - Cachan, Inria Saclay - Ile de France, CNRS - Centre National de la Recherche Scientifique : UMR8643
5 Max Planck Institute for Informatics [Saarbrücken]
6 Saarland Informatics Campus
Abstract : Naive handling of supply voltage droops in synchronous circuits results in conservative bounds on clock speeds, resulting in poor performance even if droops are rare. Adaptive strategies detect such potentially hazardous events and either initiate a rollback to a previous state or proactively reduce clock speed in order to prevent timing violations. The performance of such solutions critically depends on a very fast response to droops. However, state-of-the-art solutions incur synchronization delay to avoid that the clock signal is affected by metastability. Addressing the challenges discussed by Keith Bowman in his ASYNC 2017 keynote talk, we present an all-digital circuit that can respond to droops within a fraction of a clock cycle. This is achieved by delaying clock signals based on measurement values while they undergo synchronization simultaneously. We verify our solution by formally proving correctness, complemented by VHDL and Spice simulations of a 65 nm ASIC design confirming the theoretically obtained results.
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Matthias Függer, Attila Kinali, Christoph Lenzen, Ben Wiederhake. Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance. 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2018, Wien, Austria. ⟨hal-01936403⟩

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