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Accelerating Itemset Sampling using Satisfiability Constraints on FPGA

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Abstract

Finding recurrent patterns within a data stream is important for fields as diverse as cybersecurity or e-commerce. This requires to use pattern mining techniques. However, pattern mining suffers from two issues. The first one, known as “pattern explosion”, comes from the large combinatorial space explored and is the result of too many patterns outputed to be analyzed. Recent techniques called output space sampling solve this problem by outputing only a sampled set of all the results, with a target size provided by the user. The second issue is that most algorithms are designed to operate on static datasets or low throughput streams. In this paper, we propose a contribution to tackle both issues, by designing an FPGA accelerator for pattern mining with output space sampling. We show that our accelerator can outperform a state-of-the-art implementation on a server class CPU using a modest FPGA product.
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Dates and versions

hal-01941862 , version 1 (02-12-2018)

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Mael Gueguen, Olivier Sentieys, Alexandre Termier. Accelerating Itemset Sampling using Satisfiability Constraints on FPGA. DATE 2019 - 22nd IEEE/ACM Design, Automation and Test in Europe, Mar 2019, Florence, Italy. pp.1046-1051, ⟨10.23919/DATE.2019.8714932⟩. ⟨hal-01941862⟩
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