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Associative Instruction Reordering to Alleviate Register Pressure

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Abstract

Register allocation is generally considered a practically solved problem. For most applications, the register allocation strategies in production compilers are very effective in controlling the number of loads/stores and register spills. However, existing register allocation strategies are not effective and result in excessive register spilling for computation patterns with a high degree of many-to-many data reuse, e.g., high-order stencils and tensor contractions. We develop a source-to-source instruction reordering strategy that exploits the flexibility of reordering associative operations to alleviate register pressure. The developed transformation module implements an adaptable strategy that can appropriately control the degree of instruction-level parallelism, while relieving register pressure. The effectiveness of the approach is demonstrated through experimental results using multiple production compilers (GCC, Clang/LLVM) and target platforms (Intel Xeon Phi, and Intel x86 multi-core).
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Dates and versions

hal-01956260 , version 1 (15-12-2018)

Identifiers

  • HAL Id : hal-01956260 , version 1

Cite

Prashant Singh Rawat, Aravind Sukumaran-Rajam, Atanas Rountev, Fabrice Rastello, Louis-Noël Pouchet, et al.. Associative Instruction Reordering to Alleviate Register Pressure. SC 2018 - International Conference for High Performance Computing, Networking, Storage, and Analysis, Nov 2018, Dallas, United States. pp.1-13. ⟨hal-01956260⟩
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