From Logical Time Scheduling to Real-Time Scheduling

Frédéric Mallet 1, 2 Min Zhang 3
2 KAIROS - Logical Time for Formal Embedded System Design
CRISAM - Inria Sophia Antipolis - Méditerranée , Laboratoire I3S - COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués
Abstract : Scheduling is a central yet challenging problem in real-time embedded systems. The Clock Constraint Specification Language (CCSL) provides a formalism to specify logical constraints of events in real-time embedded systems. A prerequisite for the events is that they must be schedulable under constraints. That is, there must be a schedule which controls all events to occur infinitely often. Schedulability analysis of CCSL raises important algorithmic problems such as computational complexity and design of efficient decision procedures. In this work, we compare the scheduling problems of CCSL specifications to the real-time scheduling problem. We show how to encode a simple task model in CCSL and discuss some benefits and differences compared to more classical scheduling strategies.
Type de document :
Communication dans un congrès
39th IEEE Real-Time Systems Symposium, Dec 2018, Nashville, United States
Liste complète des métadonnées

https://hal.inria.fr/hal-01971976
Contributeur : Team Kairos <>
Soumis le : lundi 7 janvier 2019 - 14:20:26
Dernière modification le : mardi 8 janvier 2019 - 10:07:54

Identifiants

  • HAL Id : hal-01971976, version 1

Collections

Citation

Frédéric Mallet, Min Zhang. From Logical Time Scheduling to Real-Time Scheduling. 39th IEEE Real-Time Systems Symposium, Dec 2018, Nashville, United States. 〈hal-01971976〉

Partager

Métriques

Consultations de la notice

47