The low channel mobility in N-MOS 4H-SiC transistor is a major key issue for the development of power devices with satisfactory on state characteristics. Previous works have demonstrated that this low channel mobility is due to high interface state density (Dit) near the conduction band edge. Furthermore, the realization of SiC MOSFETs sustaining high reverse field necessitates thick epitaxial layer growth. An important thickness (> 30 µm) unfortunately involves important surface roughness which may result in a high interface trap density (Dit) and surface potential fluctuation (σ s) at the SiC/SiO 2 interface. In this study, we focus on SiO 2 /SiC MOS interface quality characterization as a function of process conditions and material properties (dopant type, thick layer growth technique). Investigations of the oxide quality on thick layers grown by CVD and PVT has been realized using CV under UV lightening and GV techniques. We evidenced that the Dit value (between 10 10 cm-2 .eV-1 and 9×10 10 cm-2 .eV-1 from 0.9 Ev to 0.2 eV below Ec) and σ s value (60 mV) were slightly lower for thick PVT layers. A discrepancy in the Dit values obtained from C-V and G-V measurements is attributed to the large surface potential standard deviation. Results from an original oxide growth process using a deposited sacrificial silicon layer under UHV conditions are also presented.