Priority in Logical Time Partial Orders with Synchronous Relations

Régis Gascon 1 Julien Deantoni 2 Jean-François Le Tallec 1
2 KAIROS - Logical Time for Formal Embedded System Design
CRISAM - Inria Sophia Antipolis - Méditerranée , Laboratoire I3S - COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués
Abstract : The Clock Constraint Specification Language (CCSL) offers constructs for expressing chronological and causal relations on events of an embedded system. CCSL simulator, TimeSquare allows one to visualize executions of the specified systems by determining step by step sets of synchronously occurring events. When several different sets of events are possible at a given step, the simulator uses a global simulation policy to choose one. However, this mechanism does not consider any priority between events. Inspired by priority in Petri nets, we show how to formally define a priority system supporting possibly synchronous partial orders of events. Both formal definitions and an efficient implementation are presented.
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https://hal.inria.fr/hal-02078493
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Régis Gascon, Julien Deantoni, Jean-François Le Tallec. Priority in Logical Time Partial Orders with Synchronous Relations. IEEE RIVF: Research, Innovation and Vision for the Future, Mar 2019, Danang, Vietnam. ⟨hal-02078493⟩

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