Scheduling with timed automata, Theoretical Computer Science, vol.354, issue.2, pp.272-300, 2006. ,
TIMES: A tool for schedulability analysis and code generation of real-time systems, Proc. of the 1st FORMATS, vol.2791, pp.60-72, 2003. ,
Modeling time(s), Proc. of the 10th MoDELS, vol.4735, pp.559-573, 2007. ,
, The SMT-LIB standard, 2016.
Synchronous programming with events and relations: the SIGNAL language and its semantics, Science of Computer Programming, vol.16, issue.2, pp.103-149, 1991. ,
The esterel synchronous programming language: Design, semantics, implementation, Science of Comp. Programming, vol.19, issue.2, pp.87-152, 1992. ,
URL : https://hal.archives-ouvertes.fr/inria-00075711
Software defect reduction top 10 list, Computer, vol.34, issue.1, pp.135-137, 2001. ,
Modeling flexible real time systems with preemptive time petri nets, Proc. of the 15th ECRTS, pp.279-286, 2003. ,
Lustre: A declarative language for programming synchronous systems, Proc. of 14th POPL, pp.178-188, 1987. ,
Transforming timing requirements into CCSL constraints to verify cyber-physical systems, Proc. of the 19th ICFEM, vol.10610, pp.54-70, 2017. ,
Timed-pNets: a communication behavioural semantic model for distributed systems, Frontiers of Computer Science, vol.9, issue.1, pp.87-110, 2015. ,
URL : https://hal.archives-ouvertes.fr/hal-01086091
SCADE 6: A formal language for embedded critical software development, Proc. of the 11th TASE, pp.1-11, 2017. ,
Clocks as first class abstract types, Proc. of the 3rd EMSOFT, vol.2855, pp.134-155, 2003. ,
TimeSquare: Treat your models with logical time, Proc. of the 50th TOOLS, pp.34-41, 2012. ,
URL : https://hal.archives-ouvertes.fr/hal-00688590
Model-based engineering with AADL -An introduction to the SAE architecture analysis and design language, 2012. ,
Schedulability analysis support for automotive systems: from requirement to implementation, Proc. of the 29th SAC, pp.1080-1085, 2014. ,
Decidable and undecidable problems in schedulability analysis using timed automata, Proc. of the 10th TACAS, vol.2988, pp.236-250, 2004. ,
A translation based method for the timed analysis of scheduling extended time petri nets, Prof. of the 25th RTSS, pp.187-196, 2004. ,
URL : https://hal.archives-ouvertes.fr/hal-00523591
Scheduling algorithms for multiprogramming in a hardreal-time environment, J. ACM, vol.20, issue.1, pp.46-61, 1973. ,
Boundness issues in CCSL specifications, Proc. of the 15th ICFEM, vol.8144, pp.20-35, 2013. ,
URL : https://hal.archives-ouvertes.fr/hal-00877598
, Correctness issues on MARTE/CCSL constraints. Science of Computer Programming, vol.106, pp.78-92, 2015.
MARTE for CPS and CPSoS, Cyber-Physical System Design from an Architecture Analysis Viewpoint: Communications of NII Shonan Meetings, pp.81-108, 2017. ,
URL : https://hal.archives-ouvertes.fr/hal-01671190
Safe CCSL specifications and marked graphs, Proc. of the 11th MEMOCODE, pp.157-166, 2013. ,
URL : https://hal.archives-ouvertes.fr/hal-00913962
Work-in-progress: From logical time scheduling to real-time scheduling, Proc. of the 39th RTSS, pp.143-146, 2018. ,
Z3: an efficient SMT solver, Proc. of the 14th TACAS, vol.4963, pp.337-340, 2008. ,
, OMG: UML profile for MARTE: modeling and analysis of real-time embedded systems, 2015.
PVS: A prototype verification system, Proc. of the 11th CADE, pp.748-752, 1992. ,
Clocks vs. instants relations: verifying CCSL time constraints in UML/MARTE models, Proc. of the 14th MEMOCODE, pp.78-84, 2016. ,
A generic representation of CCSL time constraints for UML/MARTE models, Proc. of the 52nd DAC, vol.122, pp.1-122, 2015. ,
Concurrency in synchronous systems, Formal Methods in System Design, vol.28, issue.2, pp.111-130, 2006. ,
URL : https://hal.archives-ouvertes.fr/inria-00071472
, Compiling Esterel, 2007.
Real time scheduling theory: A historical perspective, Real-Time Systems, vol.28, issue.2-3, pp.101-155, 2004. ,
Verifying MARTE/CCSL mode behaviors using UPPAAL, Proc. of the 11th SEFM, pp.1-15, 2013. ,
URL : https://hal.archives-ouvertes.fr/hal-00866477
Divergence detection for CCSL specification via clock causality chain, Proc. of the 2nd SETTA, pp.18-37, 2016. ,
URL : https://hal.archives-ouvertes.fr/hal-01372694
Verification of MARTE/CCSL time requirements in Promela/SPIN, Proc. of the 16th ICECCS, pp.65-74, 2011. ,
URL : https://hal.archives-ouvertes.fr/hal-00650621
Polychronous controller synthesis from MARTE/CCSL timing specifications, Proc. of the 9th MEMOCODE, pp.21-30, 2011. ,
URL : https://hal.archives-ouvertes.fr/inria-00594942
Periodic scheduling for MARTE/CCSL: Theory and practice, Science of Computer Programming, vol.154, pp.42-60, 2018. ,
URL : https://hal.archives-ouvertes.fr/hal-01670450
An executable semantics of the Clock Constraint Specification Language and its applications, Proc. of the 4th FTSCS. CCIS, vol.596, pp.37-51, 2015. ,
An SMT-based approach to the formal analysis of MARTE/CCSL, Proc. of the 18th ICFEM, vol.10009, pp.433-449, 2016. ,
URL : https://hal.archives-ouvertes.fr/hal-01394677
Towards SMT-based LTL model checking of clock constraint specification language for real-time and embedded systems, Proc. of the 18th LCTES, pp.61-70, 2017. ,