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Conference Papers Year : 2019

Evaluating the hardware cost of the posit number system

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Abstract

The posit number system is proposed as a replacement of IEEE floating-point numbers. It is a floating-point system that trades exponent bits for significand bits, depending on the magnitude of the numbers. Thus, it provides more precision for numbers around 1, at the expense of lower precision for very large or very small numbers. Several works have demonstrated that this trade-off can improve the accuracy of applications. However, the variable-length exponent and significand encoding impacts the hardware cost of posit arithmetic. The objective of the present work is to enable application-level evaluations of the posit system that include performance and resource consumption. To this purpose, this article introduces an open-source hardware implementation of the posit number system, in the form of a C++ templatized library compatible with Vivado HLS. This library currently implements addition, subtraction and multiplication for custom-size posits. In addition, the posit standard also mandates the presence of the “quire”, a large accumulator able to perform exact sums of products. The proposed library includes the first open-source parameterized hardware quire. This library is shown to improve the state-of-the-art of posit implementations in terms of latency and resource consumption. Still, standard 32 bits posit adders and multipliers are found to be much larger and slower than the corresponding floatingpoint operators. The cost of the posit 32 quire is shown to be comparable to that of a Kulisch accumulator for 32 bits floatingpoint.
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Dates and versions

hal-02130912 , version 1 (16-05-2019)
hal-02130912 , version 2 (27-06-2019)
hal-02130912 , version 3 (01-07-2019)
hal-02130912 , version 4 (24-07-2019)

Identifiers

  • HAL Id : hal-02130912 , version 4

Cite

Yohann Uguen, Luc Forget, Florent de Dinechin. Evaluating the hardware cost of the posit number system. FPL 2019 - 29th International Conference on Field-Programmable Logic and Applications (FPL), Sep 2019, Barcelona, Spain. pp.106 - 113. ⟨hal-02130912v4⟩
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