High-level synthesis of software-customizable floating-point cores, 2018. ,
, Automation & Test in Europe, pp.37-42, 2018.
LegUp: high-level synthesis for FPGA-based processor/accelerator systems, ACM/SIGDA international symposium on Field-Programmable Gate Arrays, pp.33-36, 2011. ,
Curiously recurring template patterns, vol.7, pp.24-27, 1995. ,
Designing custom arithmetic data paths with FloPoCo, IEEE Design & Test of Computers, vol.28, issue.4, pp.18-27, 2011. ,
URL : https://hal.archives-ouvertes.fr/ensl-00646282
A survey and evaluation of FPGA high-level synthesis tools, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.35, issue.10, pp.1591-1604, 2016. ,
Hardware implementation of POSITs and their application in FPGAs, International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp.138-145, 2018. ,
Fast and standalone design space exploration for high-level synthesis under resource constraints, Journal of Systems Architecture, vol.60, issue.1, pp.79-93, 2014. ,
URL : https://hal.archives-ouvertes.fr/hal-00914536
Algorithm c (AC) datatypes, 2018. ,
Templatised soft floating-point for high-level synthesis, IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2019. ,
Bridging High-Level Synthesis and Application-Specific Arithmetic: The Case Study of Floating-Point Summations, Field-Programmable Logic and Applications, 2017. ,
URL : https://hal.archives-ouvertes.fr/hal-01373954
Evaluating the hardware cost of the posit number system (Online), 2019. ,
Advanced components in the variable precision floating-point library, FCCM, pp.249-258, 2006. ,