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P. D. Vouzis, S. Collange, and M. G. Arnold, A novel cotransformation for LNS subtraction, Journal of Signal Processing Systems, vol.58, issue.1, pp.29-40, 2010.
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D. B. Thomas, Parallel generation of gaussian random numbers using the table-hadamard transform, FPGAs for Custom Computing Machines, 2013.

F. De-dinechin, M. Joldes, and B. Pasca, Automatic generation of polynomial-based hardware architectures for function evaluation, Application-specific Systems, Architectures and Processors, 2010.
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F. De-dinechin and B. Pasca, Floating-point exponential functions for DSP-enabled FPGAs, Field Programmable Technologies, pp.110-117, 2010.
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F. De-dinechin, P. Echeverría, M. López-vallejo, and B. Pasca, Floatingpoint exponentiation units for reconfigurable computing, ACM Transactions on Reconfigurable Technology and Systems, vol.6, issue.1, 2013.
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F. De-dinechin, M. Istoan, and G. Sergent, Fixed-point trigonometric functions on FPGAs, SIGARCH Computer Architecture News, vol.41, issue.5, pp.83-88, 2013.
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F. De-dinechin and M. Istoan, Hardware implementations of fixed-point Atan2, 22nd IEEE Symposium of Computer Arithmetic (ARITH-22), pp.34-41, 2015.
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D. B. Thomas, A general-purpose method for faithfully rounded floating-point function approximation in FPGAs, 22d Symposium on Computer Arithmetic, 2015.
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M. Kumm, K. Liebisch, and P. Zipf, Reduced Complexity Single and Multiple Constant Multiplication in Floating Point Precision, IEEE International Conference on Field Programmable Logic and Application (FPL), pp.255-261, 2012.
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F. De-dinechin, Multiplication by rational constants, IEEE Transactions on Circuits and Systems, vol.II, issue.2, pp.98-102, 2012.
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M. Kumm, O. Gustafsson, M. Garrido, and P. Zipf, Optimal single constant multiplication using ternary adders, IEEE Transactions on Circuits and Systems II: Express Briefs, 2016.
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H. F. Ugurdag, F. De-dinechin, Y. S. Gener, S. Gren, and L. Didier, Hardware division by small integer constants, IEEE Transactions on Computers, vol.66, issue.12, pp.2097-2110, 2017.
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H. D. Nguyen, B. Pasca, and T. Preusser, FPGA-specific arithmetic optimizations of short-latency adders, Field Programmable Logic and Applications, pp.232-237, 2011.
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N. Brunie, F. De-dinechin, M. Istoan, G. Sergent, K. Illyes et al., Arithmetic core generation using bit heaps, Field-Programmable Logic and Applications, 2013.
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M. Istoan and F. De-dinechin, Automating the pipeline of arithmetic datapaths, 2017.
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URL : https://hal.archives-ouvertes.fr/hal-01373937

A. Volkova, M. Istoan, F. De-dinechin, and T. Hilaire, Towards hardware IIR filters computing just right: Direct form I case study, IEEE Transactions on Computers, vol.68, issue.4, 2019.
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URL : https://hal.archives-ouvertes.fr/hal-01561052

M. Garrido, K. Möller, and M. Kumm, A floating-point processor for fast and accurate sine/cosine evaluation, Transactions on Circuits and Systems I: Regular Papers, vol.66, pp.1507-1516, 2019.

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S. Bansal, H. Hsiao, T. Czajkowski, and J. H. Anderson, High-level synthesis of software-customizable floating-point cores, 2018 Design, Automation & Test in Europe, pp.37-42, 2018.
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M. D. Ercegovac and T. Lang, Digital Arithmetic, 2003.
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S. Hsiao, P. Wu, C. Wen, and P. K. Meher, Table size reduction methods for faithfully rounded lookup-table-based multiplierless function evaluation, Transactions on Circuits and Systems II, vol.62, issue.5, pp.466-470, 2015.
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M. Kumm and J. Kappauf, Advanced compressor tree synthesis for FPGAs, IEEE Transactions on Computers, vol.67, issue.8, pp.1078-1091, 2018.
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Y. Uguen, F. De-dinechin, and S. Derrien, Bridging High-Level Synthesis and Application-Specific Arithmetic: The Case Study of Floating-Point Summations, 27th International Conference on Field-Programmable Logic and Applications (FPL), 2017.
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URL : https://hal.archives-ouvertes.fr/hal-01373954

S. Chevillard, M. Jolde?, and C. Lauter, Sollya: An environment for the development of numerical codes, Mathematical Software -ICMS 2010, ser, vol.6327, 2010.
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