Kilocore: A 32-nm 1000-processor computational array, IEEE Journal of Solid-State Circuits, vol.52, pp.891-902, 2017. ,
Dark silicon and the end of multicore scaling, 2011 38th Annual International Symposium on Computer Architecture (ISCA), pp.365-376, 2011. ,
Architecture support for accelerator-rich cmps, DAC Design Automation Conference, pp.843-849, 2012. ,
The accelerator store framework for high-performance, low-power accelerator-based systems, IEEE Computer Architecture Letters, vol.9, pp.53-56, 2010. ,
, Processor and System-on-Chip Simulation, 2010.
The Gem5 Simulator, SIGARCH Comput. Archit. News, vol.39, pp.1-7, 2011. ,
HAPS ® Family of FPGA-Based Prototyping Solutions, 2014. ,
A Case for FAME: FPGA Architecture Model Execution, Proceedings of the 37th Annual International Symposium on Computer Architecture, pp.290-301, 2010. ,
GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms, Proceedings of the 2011 11th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing, pp.53-62, 2011. ,
Codesigning accelerators and soc interfaces using gem5-aladdin, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp.1-12, 2016. ,
The aladdin approach to accelerator design and modeling, IEEE Micro, vol.35, pp.58-70, 2015. ,
A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs, ACM Trans. Reconfigurable Technol. Syst, vol.2, pp.1-16, 2009. ,
Llvm: a compilation framework for lifelong program analysis transformation, International Symposium on Code Generation and Optimization, pp.75-86, 2004. ,
Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), pp.97-108, 2014. ,
Risc-v, rocket, and rocc, 2017. ,
BSV by Example: The Next-generation Language for Electronic System Design, 2010. ,
The RISC-V Instruction Set Manual, vol.I, 2014. ,
The LEAP FPGA Operating System, 2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp.1-8, 2014. ,
Awb: The asim architect's workbench, 3rd Annual Workshop on Modeling, Benchmarking, and Simulation, 2007. ,
The cache performance and optimizations of blocked algorithms, Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS IV, pp.63-74, 1991. ,
Machsuite: Benchmarks for accelerator design and customized architectures, 2014 IEEE International Symposium on Workload Characterization (IISWC), pp.110-119, 2014. ,
RAMP Gold: An FPGA-based Architecture Simulator for Multiprocessors, Proceedings of the 47th Design Automation Conference, pp.463-468, 2010. ,
HAsim: FPGA-Based High-Detail Multicore Simulation Using Time-Division Multiplexing, 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA), pp.406-417, 2011. ,
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators, Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, pp.249-261, 2007. ,
A very fast trace-driven simulation platform for chip-multiprocessors architectural explorations, IEEE Transactions on Parallel and Distributed Systems, vol.28, pp.3033-3045, 2017. ,
Parade: A cycle-accurate full-system simulation platform for accelerator-rich architectural design and exploration, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp.380-387, 2015. ,
Designing domain-specific heterogeneous architectures from dataflow programs, Computers, vol.7, p.27, 2018. ,