Compressed cache layout aware prefetching

Niloofar Charmchi 1 Caroline Collange 1 André Seznec 1
1 PACAP - Pushing Architecture and Compilation for Application Performance
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Keywords : hardware prefetching compaction cache compression
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Conference papers
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https://hal.inria.fr/hal-02316773
Contributor : Caroline Collange <>
Submitted on : Tuesday, October 15, 2019 - 3:32:37 PM
Last modification on : Tuesday, October 22, 2019 - 9:46:37 AM
Long-term archiving on: Friday, January 17, 2020 - 10:01:26 AM

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  • HAL Id : hal-02316773, version 1

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UNIV-RENNES1 | CNRS | CENTRALESUPELEC | INRIA | UNIV-RENNES | IRISA | UR1-UFR-ISTIC

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Niloofar Charmchi, Caroline Collange, André Seznec. Compressed cache layout aware prefetching. SBAC-PAD 2019 - International Symposium on Computer Architecture and High Performance Computing, Oct 2019, Campo Grande, MS, Brazil. pp.1-4. ⟨hal-02316773⟩

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