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Compressed cache layout aware prefetching

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Computer Science [cs] Hardware Architecture [cs.AR]
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Caroline Collange  : Connect in order to contact the contributor

https://hal.inria.fr/hal-02316773

Submitted on : Tuesday, October 15, 2019-3:32:37 PM

Last modification on : Wednesday, February 8, 2023-5:11:09 PM

Long-term archiving on: Friday, January 17, 2020-10:01:26 AM

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hal-02316773 , version 1 (15-10-2019)

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  • HAL Id : hal-02316773 , version 1

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Niloofar Charmchi, Caroline Collange, André Seznec. Compressed cache layout aware prefetching. SBAC-PAD 2019 - International Symposium on Computer Architecture and High Performance Computing, Oct 2019, Campo Grande, MS, Brazil. pp.1-4. ⟨hal-02316773⟩

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UNIV-RENNES1 CNRS INRIA INSA-RENNES IRISA CENTRALESUPELEC INRIA2 UR1-MATH-STIC UR1-UFR-ISTIC UNIV-RENNES UR1-MATH-NUM
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