, , 2011.
Clustered Voltage Scaling Technique for Low-Power Design, Proc. of the International Symposium on Low Power Design (ISLPED), pp.3-8, 1995. ,
The Current-Mirror Amplifier, VLSI Memory Chip Design, pp.84-87, 2001. ,
, , 2007.
Pushing ASIC Performance in a Power Envelope, Proc. of the 40th Design Automation Conference (DAC), pp.788-793, 2003. ,
Level-shifter-less Approach for Multi-VDD Design to use Body Bias Control in FD-SOI, Proc. of the 25th IFIP/IEEE International Conference on Very Large Scale Integration, 2017. ,
On Gate Level Power Optimization Using Dual-Supply Voltages, IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol.9, issue.5, pp.616-645, 2001. ,
Enhanced Clustered Voltage Scaling for Low Power, Proc. of the 12th ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.18-23, 2002. ,
A Top-Down Low Power Design Technique Using Clustered Voltage Scaling with Variable Supply-Voltage Scheme, Proc. of the IEEE Custom Integrated Circuits Conference (CICC), pp.495-498, 1998. ,
Level Conversion for Dual-Supply Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.12, pp.185-195, 2004. ,
Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages, Proc. of the 18th International Conference on VLSI Design (VLSID), 2005. ,
Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.13, pp.1103-1107, 2005. ,
Low Power and High Speed Multi Threshold Voltage Interface Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.17, pp.638-645, 2009. ,
Silicon on Thin BOX: A New Paradigm of The CMOSFET for Low-Power and High-Performance Application Featuring Wide-Range Back-Bias Control, IEEE International Electron Devices Meeting (IEDM) Technical Digest, 2004. ,
Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37 V Utilizing Adaptive Back Bias, Symposium on VLSI Technology, 2013. ,
Level Converter Design for Ultra-low Voltage Operation in FDSOI Devices, Proc. of the 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2014. ,
Design and Control Methodology for Fine Grain Power Gating based on Energy Characterization and Code Profiling of Microprocessors, Proc. of the 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.843-848, 2014. ,
Level-shifter Free Approach for Multi-VDD SOTB employing Adaptive Vt Modulation for pMOSFET, Proc. of the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017. ,