S. Avramenko,

M. Sonza-reorda,

M. Violante,

G. Fey and ;. Mess,

R. Schmidt, On the robustness of DCT-based compression algorithms for space applications, IEEE 22nd International Symposium on On-Line Testing and Robust System Design, 2016.

M. , COTS-based applications in space avionics, 2010 Design, Automation & Test in Europe Conference & Exhibition, 2010.

. Ute-fides-guide, , 2009.

M. Psarakis, Microprocessor Software-Based Self-Testing, IEEE Design & Test of Computers, vol.27, issue.3, pp.4-19, 2010.

R. Cantoro, A. Firrincieli, D. Piumatti, E. Sanchez, M. Sonza-reorda et al., About functionally untestable fault identification in microprocessor cores for safety-critical applications, IEEE Latin-American Test Symposium (LATS), 2018.

N. Kranitis and ;. Merentitis,

G. Theodorou,

A. Paschalis,

D. Gizopoulos, Hybrid-SBST Methodology for Efficient Testing of Processor Cores, IEEE Design & Test of Computers, issue.1, pp.64-75, 2008.

J. Mess, R. Schmidt, and G. Fey, Adaptive Compression Schemes for Housekeeping Data, 2017 IEEE Aerospace Conference

P. Bernardi, M. Bonazza, E. Sanchez, M. Sonza-reorda, and O. Ballan, On-line functionally untestable fault identification in embedded processor cores, Proc. Design, Autom. Test Eur. Conf. Exhibit. (DATE), pp.1462-1467, 2013.

W. M. Globe, Control Systems Safety Evaluation and Reliability

J. Raik, H. Fujiwara, R. Ubar, and A. Krivenko, Untestable Fault Identification in Sequential Circuits Using Model-Checking, Proc. IEEE Asian Test Symposium, pp.21-26, 2008.

M. Syal and M. S. Hsiao, New techniques for untestable fault identification in sequential circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.5, issue.6, pp.1117-1131, 2006.

H. L. Liang;-c and . Lee,

J. E. Chen, Identifying Untestable Faults in Sequential Circuits, IEEE Design & Test of Computers, vol.12, issue.3, pp.14-23, 1995.

W. Lai,

A. Krstic, . Kwang-ting, and . Cheng, Functionally testable path delay faults on a microprocessor, IEEE Design & Test of Computers, vol.17, issue.4, pp.6-14, 2000.

A. Riefert;-r and . Cantoro,

M. Sauer,

M. Sonza-reorda,

B. Becker, A Flexible Framework for the Automatic Generation of SBST Programs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.3055-3066, 2016.

D. E. Long, M. A. Iyer, and M. Abramovici, FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults, ACM Transactions on Design Automation of Electronic Systems (TODAES), pp.631-657, 2000.

D. Tille and R. Drechsler, A fast untestability proof for SAT-based ATPG, 12th International Symposium on Design and Diagnostics of Electronic Cir-cuits&Systems, pp.38-43, 2009.

S. Carbonara, A. Firrincieli, M. Sonza-reorda, and J. Mess, On the test of a COTS-based system for space applications, 24th IEEE International Symposium on On-Line Testing and Robust System Design, 2018.

, Jaroslav Borecky

M. Kohlik,

P. Kubalik,

H. Kubatova, Fault Models Usability Study for On-line Tested FPGA, 14th Euromicro Conference on Digital System Design, pp.287-290, 2011.

D. Sabena, M. Sonza-reorda, and L. Sterpone, A new SBST algorithm for testing the register file of VLIW processors, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.412-417, 2012.

A. Apostolakis, M. Psarakis, D. Gizopoulos, and A. Paschalis, Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.15, pp.971-975, 2007.

R. Cantoro, S. Carbonara, A. Floridia, E. Sanchez, M. S. Reorda et al., An analysis of test solutions for COTS-based systems in space applications, 2018.

, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp.59-64, 2018.

M. Bushnell and V. , Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits, 2000.