Skip to Main content Skip to Navigation
Conference papers

Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis

Abstract : This work deals with the optimization of Deep Convolutional Neural Networks (ConvNets). It elaborates on the concept of Adaptive Energy-Accuracy Scaling through multi-precision arithmetic, a solution that allows ConvNets to be adapted at run-time and meet different energy budgets and accuracy constraints. The strategy is particularly suited for embedded applications made run at the “edge” on resource-constrained platforms. After the very basics that distinguish the proposed adaptive strategy, the paper recalls the software-to-hardware vertical implementation of precision scalable arithmetic for ConvNets, then it focuses on the energy-driven per-layer precision assignment problem describing a meta-heuristic that searches for the most suited representation of both weights and activations of the neural network. The same heuristic is then used to explore the optimal trade-off providing the Pareto points in the energy-accuracy space. Experiments conducted on three different ConvNets deployed in real-life applications, i.e. Image Classification, Keyword Spotting, and Facial Expression Recognition, show adaptive ConvNets reach better energy-accuracy trade-off w.r.t. conventional static fixed-point quantization methods.
Document type :
Conference papers
Complete list of metadata

Cited literature [42 references]  Display  Hide  Download
Contributor : Hal Ifip Connect in order to contact the contributor
Submitted on : Monday, October 21, 2019 - 2:55:02 PM
Last modification on : Thursday, December 2, 2021 - 12:17:34 PM
Long-term archiving on: : Wednesday, January 22, 2020 - 6:01:12 PM


Files produced by the author(s)


Distributed under a Creative Commons Attribution 4.0 International License



Valentino Peluso, Andrea Calimera. Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis. 26th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2018, Verona, Italy. pp.107-127, ⟨10.1007/978-3-030-23425-6_6⟩. ⟨hal-02321763⟩



Record views


Files downloads