Skip to Main content Skip to Navigation
Conference papers

ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code

Abstract : Error resilient high speed robust data communication is the primary need in the age of big data and Internet-of-things (IoT), where multiple connected devices exchange huge amount of information. Different multi-bit error detecting and correcting codes are used for error mitigation in the high speed data communication though it introduces delay and their decoding structures are quite complex. Here we have discussed the implementation of single bit error correcting Bose, Chaudhuri, Hocquenghem (BCH) code with simple decoding structure on a state-of-the art ReRAM based in-memory computing platform. ReRAM devices offer low leakage power, high endurance and non-volatile storage capabilities, coupled with stateful logic operations. The proposed lightweight library presents the mapping for generation of elements on Galois field (GF) for computation of BCH code, along with encoding and decoding operations on input data stream using BCH code. We have verified the results for BCH code with different dimensions using SPICE simulation. For (15,11) BCH code, the number of clock cycles required for element generation, decoding and encoding of BCH code are 103, 230 and 251 respectively, which demonstrates the efficacy of the mapping.
Document type :
Conference papers
Complete list of metadata

Cited literature [32 references]  Display  Hide  Download
Contributor : Hal Ifip <>
Submitted on : Monday, October 21, 2019 - 2:55:09 PM
Last modification on : Monday, October 21, 2019 - 3:10:10 PM
Long-term archiving on: : Wednesday, January 22, 2020 - 4:04:18 PM


 Restricted access
To satisfy the distribution rights of the publisher, the document is embargoed until : 2022-01-01

Please log in to resquest access to the document


Distributed under a Creative Commons Attribution 4.0 International License



Yaswanth Tavva, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Swagata Mandal. ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code. 26th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2018, Verona, Italy. pp.128-146, ⟨10.1007/978-3-030-23425-6_7⟩. ⟨hal-02321764⟩



Record views