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A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load

Abstract : A synthesizable digital LDO implemented with standard-cell-based digital design flow is proposed. The difference between output and reference voltages is converted into delay difference using inverter chains as voltage-controlled delay lines, then compared in the time-domain. Since the time-domain difference is straightforwardly captured by a simple DFF-based phase detector, the proposed LDO does not need an analog voltage comparator, which requires careful manual design. All the components in the LDO can be described with Verilog codes based on their specifications, and placed-and-routed with a commercial EDA tool. This automated layout design relaxes the burden and time of implementation, and enhances process portability. The proposed LDO implemented in a 65 nm standard CMOS technology occupies 0.015 mm$^2$ area. With 10.4 MHz internal clock, the tracking response of the LDO to 200 mV switching in the reference voltage is $\sim $4.5 $µ$s and the transient response to 5 mA change in the load current is $\sim $6.6 $µ$s. At 10 mA load current, the quiescent current consumed by the LDO core is as low as 35.2 $µ$A, which leads to 99.6% current efficiency.
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https://hal.inria.fr/hal-02321770
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Submitted on : Monday, October 21, 2019 - 2:55:21 PM
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Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada. A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. 26th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2018, Verona, Italy. pp.1-13, ⟨10.1007/978-3-030-23425-6_1⟩. ⟨hal-02321770⟩

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