A. Bhattacharya, S. Pal, and A. Islam, Implementation of finfet based stt-mram bitcell, 2014 IEEE International Conference on Advanced Communications. Control and Computing Technologies, pp.435-439, 2014.

, ITRS International Technology Roadmap for Semiconductor

Y. Liu and Q. Xu, On modeling faults in FinFET logic circuits, IEEE International Test Conference, pp.1-9, 2012.

G. Harutyunyan, G. Tshagharyan, V. Vardanian, and Y. Zorian, Fault modeling and test algorithm creation strategy for FinFET-based memories, IEEE 32nd VLSI Test Symposium (VTS), pp.1-6, 2014.

F. Mesalles, H. Villacorta, M. Renovell, and V. Champac, Behavior and test of opengate defects in FinFET based cells, 21th IEEE European Test Symposium (ETS), pp.1-6, 2016.
URL : https://hal.archives-ouvertes.fr/lirmm-01923016

G. Panagopoulos, C. Augustine, and K. Roy, Modeling of dielectric breakdowninduced time-dependent STT-MRAM performance degradation, Proc. DRC, pp.125-126, 2011.

R. Bishnoi, F. Oboril, and M. B. Tahoori, Design of defect and fault-tolerant nonvolatile spintronic flip-flops, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1421-1432, 2017.

A. Chintaluri, A. Parihar, S. Natarajan, H. Naeimi, and A. Raychowdhury, A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays, 2015 IEEE 24th Asian Test Symposium (ATS), pp.187-192, 2015.

A. Chintaluri, H. Naeimi, S. Natarajan, and A. Raychowdhury, Analysis of defects and variations in embedded spin transfer torque (stt) mram arrays, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol.6, issue.3, pp.319-329, 2016.

. Diao, Spin-transfer torque switching in magnetic tunnel junctions and spintransfer torque random access memory, Journal of Physics: Condensed Matter, vol.19, issue.16, p.165209, 2007.

E. I. Vatajelu, P. Prinetto, M. Taouil, and S. Hamdioui, Challenges and Solutions in Emerging Memory Testing, IEEE Transactions on Emerging Topics in Computing, 2017.
URL : https://hal.archives-ouvertes.fr/hal-01528655

L. Wu, M. Taouil, S. Rao, E. J. Marinissen, and S. Hamdioui, 2018 IEEE International Test Conference (ITC), pp.1-10, 2018.

R. Bishnoi, M. Ebrahimi, F. Oboril, and M. B. Tahoori, Read disturb fault detection in STT-MRAM, pp.1-7, 2014.

A. F. Gomez, F. Forero, K. Roy, and V. Champac, Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations, 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp.65-70, 2018.
URL : https://hal.archives-ouvertes.fr/hal-02321772

A. F. Gomez, F. Lavratti, G. Medeiros, M. Sartori, L. Bolzani-poehls et al., Effectiveness of a hardware-based approach to detect resistiveopen defects in sram cells under process variations. Microelectronics Reliability, vol.67, pp.150-158, 2016.

M. Hosomi, A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram, IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest, pp.459-462, 2005.

T. Andre, ST-MRAM fundamentals, challenges, and applications, In: Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, pp.1-8, 2013.

X. Fong, Y. Kim, R. Venkatesan, S. H. Choday, A. Raghunathan et al., Spin-transfer torque memories: Devices, circuits, and systems, Proceedings of the IEEE, pp.1449-1488, 2016.

M. Baibich and . Norberto, Giant magnetoresistance of (001) Fe/(001) Cr magnetic superlattices, Physical review letters pp, p.2472, 1988.

S. Yuasa, T. Nagahama, A. Fukushima, Y. Suzuki, A. et al., Giant room-temperature magnetoresistance in single-crystal Fe/MgO/Fe magnetic tunnel junctions, Nature materials, vol.3, issue.12, p.868, 2004.

X. Fong, S. H. Choday, and K. Roy, Bit-cell level optimization for non-volatile memories using magnetic tunnel junctions and spin-transfer torque switching, IEEE Transactions on Nanotechnology, vol.11, issue.1, pp.172-181, 2012.

M. Hosomi, A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram, IEEE International Electron Devices Meeting, pp.459-462, 2005.

X. Fong, P. Sri-harsha-choday, C. Georgios, K. Augustine, and . Roy, Spice models for magnetic tunnel junctions based on monodomain approximation, 2013.

Y. Zhang, X. Wang, Y. Li, A. K. Jones, and Y. Chen, Asymmetry of mtj switching and its implication to stt-ram designs, 2012 Design, Automation Test in Europe Conference Exhibition (DATE), pp.1313-1318, 2012.

Y. Zhang, X. Wang, H. Li, and Y. Chen, STT-RAM Cell Optimization Considering MTJ and CMOS Variations, pp.2962-2965, 2011.

Y. Emre, C. Yang, K. Sutaria, Y. Cao, and C. Chakrabarti, Enhancing the Reliability of STT-RAM through Circuit and System Level Techniques, IEEE Workshop on Signal Processing Systems, pp.125-130, 2012.

S. Motaman, . Ghosh, . Swaroop, and N. Rathi, Impact of Process-variations in STTRAM and Adaptive Boosting for Robustness, Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, pp.1431-1436, 2015.

, Predictive technology models

F. Forero, J. Galliere, M. Renovell, and V. Champac, Detectability challenges of bridge defects in finfet based logic cells, Journal of Electronic Testing, vol.34, issue.2, pp.123-134, 2018.