L. F. Abbott, Lapicque's introduction of the integrate-and-fire model neuron, Brain research bulletin, vol.50, issue.5, pp.303-304, 1907.

, Real-time scalable cortical computing at 46 giga-synaptic ops/watt with 100x speedup in time-to-solution and 100,000x reduction in energy-tosolution, SC14: International Conference for High Performance Computing, Networking, Storage and Analysis, pp.27-38, 2014.

F. Barchi, G. Urgese, A. Acquaviva, and E. Macii, Directed graph placement for snn simulation into a multi-core gals architecture, 2018 IFIP/IEEE International Conference on Very Large Scale Integration, pp.19-24, 2018.

F. Chung, Laplacians and the cheeger inequality for directed graphs, Annals of Combinatorics, vol.9, issue.1, pp.1-19, 2005.

M. E. Davies, Loihi: A neuromorphic manycore processor with on-chip learning, IEEE Micro, vol.38, issue.1, pp.82-99, 2018.

A. P. Davison, Pynn: a common interface for neuronal network simulators, Frontiers in neuroinformatics, vol.2, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00586786

C. M. Fiduccia and R. M. Mattheyses, A linear-time heuristic for improving network partitions, Papers on Twenty-five years of electronic design automation, pp.241-247, 1988.

S. B. Furber, The spinnaker project, Proceedings of the IEEE, vol.102, issue.5, pp.652-665, 2014.

S. E. Furber, On-chip and inter-chip networks for modeling large-scale neural systems, Proceedings. 2006 IEEE International Symposium on, p.4, 2006.

N. E. Gibbs, A comparison of several bandwidth and profile reduction algorithms, ACM Transactions on Mathematical Software (TOMS), vol.2, issue.4, pp.322-330, 1976.

E. M. Izhikevich, Simple model of spiking neurons, IEEE Transactions on neural networks, vol.14, issue.6, pp.1569-1572, 2003.

X. Jin, S. Furber, and J. Woods, Efficient modelling of spiking neural networks on a scalable chip multiprocessor, IEEE International Joint Conference on, pp.2812-2819, 2008.

X. Jin, Algorithm and software for simulation of spiking neural networks on the multi-chip spinnaker system, The 2010 International Joint Conference on, pp.1-8, 2010.

G. Karypis and V. Kumar, A fast and high quality multilevel scheme for partitioning irregular graphs, SIAM Journal on scientific Computing, vol.20, issue.1, pp.359-392, 1998.

S. E. Kirkpatrick, Optimization by simulated annealing, science, vol.220, issue.4598, pp.671-680, 1983.

C. Liu, G. Bellec, B. Vogginger, D. Kappel, J. Partzsch et al., Memory-efficient deep learning on a spinnaker 2 prototype, Frontiers in neuroscience, vol.12, 2018.

W. Maass, Networks of spiking neurons: the third generation of neural network models, Neural networks, vol.10, issue.9, pp.1659-1671, 1997.

Z. Á. Mann, Multicore-aware virtual machine placement in cloud data centers, IEEE Transactions on Computers, vol.65, issue.11, pp.3357-3369, 2016.

F. Pellegrini, Static mapping by dual recursive bipartitioning of process architecture graphs, Scalable High-Performance Computing Conference, pp.486-493, 1994.

F. Pellegrini, A parallelisable multi-level banded diffusion scheme for computing balanced partitions with smooth boundaries, European Conference on Parallel Processing, pp.195-204, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00301427

T. C. Potjans, The cell-type specific cortical microcircuit: relating structure and activity in a full-scale spiking network model, Cerebral cortex, vol.24, issue.3, pp.785-806, 2014.

A. Rast, A. Stokes, A. Rowley, S. Davies, D. Lester et al., Aer intersystem exchange protocol, 2015.

O. Rhodes, P. A. Bogdan, C. Brenninkmeijer, S. Davidson, D. Fellows et al., spynnaker: A software package for running pynn simulations on spinnaker, vol.12, 2018.

, A fast and accurate technique for mapping parallel applications on stream-oriented mpsoc platforms with communication awareness, International Journal of Parallel Programming, vol.36, issue.1, pp.3-36, 2008.

J. W. Sammon, A nonlinear mapping for data structure analysis, IEEE Transactions on computers, vol.100, issue.5, pp.401-409, 1969.

A. Siino, F. Barchi, S. Davies, G. Urgese, and A. Acquaviva, Data and commands communication protocol for neuromorphic platform configuration, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC), pp.23-30, 2016.

I. E. Sugiarto, Optimized task graph mapping on a many-core neuromorphic supercomputer, High Performance Extreme Computing Conference (HPEC, pp.1-7, 2017.

G. Urgese, F. Barchi, and E. Macii, Top-down profiling of application specific manycore neuromorphic platforms, IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-15) (IEEE MCSoC-15), 2015.

G. Urgese, F. Barchi, E. Macii, and A. Acquaviva, Optimizing network traffic for spiking neural network simulations on densely interconnected many-core neuromorphic platforms, IEEE Transactions on Emerging Topics in Computing, issue.99, 2016.

S. J. Van-albada, Full-scale simulation of a cortical microcircuit on spinnaker, Front. Neuroinform. Conference Abstract: Neuroinformatics, vol.10, 2016.

S. Van-dongen, Graph clustering via a discrete uncoupling process, SIAM Journal on Matrix Analysis and Applications, vol.30, issue.1, pp.121-141, 2008.