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Conference Papers Year : 2019

An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication

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Abstract

This chapter presents an instruction set architecture (ISA) dedicated to the rapid and efficient implementation of single-channel IoT communication interfaces. The architecture is meant to provide a programming interface for the implementation of signaling protocols based on the recently introduced pulsed-index schemes. In addition to the traditional aspects of ISA design such as addressing modes, instruction types, instruction formats, registers, interrupts, and external I/O, the ISA includes special-purpose instructions that facilitate bit stream encoding and decoding based on the pulsed-index techniques. Verilog HDL is used to synthesize a fully functional processor based on this ISA and provide both an FPGA implementation and a synthesised ASIC design in GLOBALFOUNDRIES 65 nm. The ASIC design confirms the low-power features of this ISA with consumed power around 31 $µ$ W and energy efficiency of less than 10 pJ/bit. Finally, this chapter shows how the basic ISA can be extended to include cryptographic features in support of secure IoT communication.
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Dates and versions

hal-02321776 , version 1 (21-10-2019)

Licence

Attribution - CC BY 4.0

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Shahzad Muzaffar, Ibrahim Elfadel. An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication. 26th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2018, Verona, Italy. pp.14-31, ⟨10.1007/978-3-030-23425-6_2⟩. ⟨hal-02321776⟩
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