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What You Simulate Is What You Synthesize: Design of a RISC-V Core from C++ Specifications

Simon Rokicki 1 Davide Pala 1 Joseph Paturel 1 Olivier Sentieys 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
IRISA-D3 - ARCHITECTURE, Inria Rennes – Bretagne Atlantique
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https://hal.inria.fr/hal-02394911
Contributor : Olivier Sentieys Connect in order to contact the contributor
Submitted on : Thursday, December 5, 2019 - 10:04:50 AM
Last modification on : Thursday, November 4, 2021 - 10:54:02 AM
Long-term archiving on: : Friday, March 6, 2020 - 1:58:53 PM

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  • HAL Id : hal-02394911, version 1

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UNIV-RENNES1 | CENTRALESUPELEC | INRIA | UNIV-RENNES | IRISA | CNRS | UR1-MATH-STIC | UR1-UFR-ISTIC | INSA-RENNES | UR1-MATH-NUM

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Simon Rokicki, Davide Pala, Joseph Paturel, Olivier Sentieys. What You Simulate Is What You Synthesize: Design of a RISC-V Core from C++ Specifications. RISC-V Workshop 2019, Jun 2019, Zurich, Switzerland. pp.1-2. ⟨hal-02394911⟩

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