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Using Model Checking to Identify Timing Interferences on Multicore Processors

Viet Anh Nguyen 1 Eric Jenn 1 Wendelin Serwe 2 Frederic Lang 2 Radu Mateescu 2
1 IRT Saint Exupéry - Institut de Recherche Technologique
2 CONVECS - Construction of verified concurrent systems
Inria Grenoble - Rhône-Alpes, LIG - Laboratoire d'Informatique de Grenoble
Keywords : AURIX TriCore CADP Model checking Timing interference Index Terms Multicore
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https://hal.inria.fr/hal-02462085
Contributor : Radu Mateescu <>
Submitted on : Friday, January 31, 2020 - 9:57:39 AM
Last modification on : Tuesday, November 24, 2020 - 4:00:15 PM
Long-term archiving on: : Friday, May 1, 2020 - 1:02:57 PM

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  • HAL Id : hal-02462085, version 1

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LIG | LIG_MFML_CONVECS | INRIA | CONVECS | IRT_SAINT-EXUPERY | ERTS2020 | CNRS | UGA

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Viet Anh Nguyen, Eric Jenn, Wendelin Serwe, Frederic Lang, Radu Mateescu. Using Model Checking to Identify Timing Interferences on Multicore Processors. ERTS 2020 - 10th European Congress on Embedded Real Time Software and Systems, Jan 2020, Toulouse, France. pp.1-10. ⟨hal-02462085⟩

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