D. Kästner, M. Schlickling, M. Pister, C. Cullmann, G. Gebhard et al., Meeting Real-Time Requirements with Multi-core Processors, Computer Safety, Reliability, and Security, vol.7613, pp.117-131, 2012.

H. Garavel, F. Lang, and W. Serwe, From LOTOS to LNT," in ModelEd, TestEd, TrustEd -Essays Dedicated to Ed Brinksma on the Occasion of His 60th Birthday, ser, LNCS, vol.10500, pp.3-26, 2017.

R. Mateescu and D. Thivolle, A Model Checking Language for Concurrent Value-Passing Systems, FM 2008: Formal Methods, vol.5014, pp.148-164, 2008.
URL : https://hal.archives-ouvertes.fr/inria-00315312

H. Garavel, F. Lang, R. Mateescu, and W. Serwe, CADP 2011: A Toolbox for the Construction and Analysis of Distributed Processes, Springer International Journal on Software Tools for Technology Transfer (STTT), vol.15, pp.89-107, 2013.
URL : https://hal.archives-ouvertes.fr/hal-00715056

X. Jean, Maîtrise de la couche hyperviseur sur les architectures multi-coeurs COTS dans un contexte avionique, 2015.

, Certification Authorities Software Team (CAST), 2016.

. Thales-avionics, The use of multicore processors in airbone systems, 2011.

S. Girbal, J. Le-rhun, and H. Saoud, Metrics: A Measurement Environment For Multi-Core Time Critical Systems, Zenodo, 2018.
URL : https://hal.archives-ouvertes.fr/hal-02278292

P. Bieber, F. Boniol, Y. Bouchebaba, J. Brunel, C. Pagetti et al., Phylog -etude de la certificabilité des architectures logicielmatériel reposant sur des calculateurs multi/many-core, ONERA, Tech. Rep, 2017.

W. Sun, E. Jenn, and T. Carle, Automatic Identification of Timing Interferences on Multi-Core Processors in a Model-Based Approach

M. Lv, W. Yi, N. Guan, and G. Yu, Combining Abstract Interpretation with Model Checking for Timing Analysis of Multicore Software, 2010 31st IEEE Real-Time Systems Symposium, pp.339-349, 2010.

A. Gustavsson, A. Ermedahl, B. Lisper, and P. Pettersson, Towards WCET analysis of multicore architectures using UPPAAL, 10th international workshop on worst-case execution time analysis (WCET 2010). Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik, 2010.

G. Fernandez, J. Abella, E. Quiñones, C. Rochange, T. Vardanega et al., Contention in multicore hardware shared resources: Understanding of the state of the art, 14th International Workshop on Worst-Case Execution Time Analysis. Schloss Dagstuhl-Leibniz-Zentrum für Informatik, 2014.

, AURIX TC27x D-Step 32-Bit Single-Chip Microcontroller User's Manual V2, vol.2, pp.2014-2026

D. Champelovier, X. Clere, H. Garavel, Y. Guerte, F. Lang et al., Reference manual of the lnt to lotos translator, 2018.

F. Lang, Open 2.0: A Flexible Tool Integrating Partial Order, Compositional, and On-The-Fly Verification Methods, Integrated Formal Methods, vol.3771, pp.70-88, 2005.
URL : https://hal.archives-ouvertes.fr/hal-01957351

H. Garavel and F. Lang, SVL: a Scripting Language for Compositional Verification, Proceedings of the 21st IFIP WG 6.1 International Conference on Formal Techniques for Networked and Distributed Systems (FORTE'01), pp.377-392, 2001.
URL : https://hal.archives-ouvertes.fr/inria-00072396

H. Garavel, F. Lang, and R. Mateescu, Compositional verification of asynchronous concurrent systems using CADP, Acta Informatica, vol.52, issue.4-5, pp.337-392, 2015.
URL : https://hal.archives-ouvertes.fr/hal-01138749

D. Chabrol, V. David, P. Oudin, G. Zeppa, and M. Jan, Freedom from interference among time-triggered and angle-triggered tasks: a powertrain case study, 2014.
URL : https://hal.archives-ouvertes.fr/hal-02272222

H. Cassé and P. Sainrat, OTAWA, a framework for experimenting WCET computations, 3rd European Congress on Embedded Real-Time Software, vol.1, 2006.

B. Pagano, C. Pasteur, G. Siegel, and R. Knizek, A Model Based Safety Critical Flow for the AURIX(tm) Multi-core Platform, 2018.