A. Bailey, G. A. Mccaskill-&-george, and J. Milne, An exercise in the automatic verification of asynchronous designs, Formal Methods in System Design, vol.4, issue.3, pp.213-242, 1994.

E. Beigné, F. Clermidy, P. Vivet, and A. Clouard-&-marc-renaudin, An Asynchronous NoC Architecture Providing Low Latency Service and Its Multi-Level Design Framework, Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems ASYNC'05, pp.54-63, 2005.

D. Bergamini, N. Descoubes, and C. Mateescu, BISIMULATOR: A Modular Tool for On-the-Fly Equivalence Checking, Proceedings of the 11th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS'05), vol.3440, pp.581-585, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00685325

J. Kees-van-berkel, M. Kessels, and . Roncken, The VLSI-Programming Language Tangram and its Translation into Handshake Circuits, Proceedings of the Conference on European Design Automation, pp.384-389, 1991.

A. Bouzafour, M. Renaudin, and H. Garavel, Modelchecking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits, Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'18), pp.34-42, 2018.
URL : https://hal.archives-ouvertes.fr/hal-01777093

D. Stephen, C. A. Brookes, . W. Hoare-&-a, and . Roscoe, A Theory of Communicating Sequential Processes, Journal of the ACM, vol.31, issue.3, pp.560-599, 1984.

D. Champelovier, X. Clerc, H. Garavel, Y. Guerte, C. Mckinty et al., Reference Manual of the LNT to LOTOS Translator (Version 6.8), Wendelin Serwe & Gideon Smeding, 2019.

R. Cleaveland, J. Parrow, and &. Steffen, The Concurrency Workbench, Proceedings of the 1st Workshop on Automatic Verification Methods for Finite State Systems, vol.407, pp.24-37, 1989.

D. L. Dill, Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits, 1988.

D. Edwards and &. Bardsley, Balsa: An Asynchronous Hardware Synthesis Language, The Computer Journal, vol.45, issue.1, pp.12-18, 2002.

H. Garavel and &. Lang, SVL: a Scripting Language for Compositional Verification, Proceedings of the 21st IFIP WG 6.1 International Conference on Formal Techniques for Networked and Distributed Systems (FORTE'01), pp.377-392, 2001.
URL : https://hal.archives-ouvertes.fr/inria-00072396

H. Garavel and F. Lang, CADP 2011: A Toolbox for the Construction and Analysis of Distributed Processes. Springer International Journal on Software Tools for Technology Transfer (STTT), vol.15, pp.89-107, 2013.
URL : https://hal.archives-ouvertes.fr/hal-00715056

H. Garavel and F. Lang-&-wendelin-serwe, From LOTOS to LNT, ModelEd, TestEd, TrustEd -Essays Dedicated to Ed Brinksma on the Occasion of His 60th Birthday, vol.10500, pp.3-26, 2017.
URL : https://hal.archives-ouvertes.fr/hal-01621670

H. Garavel-&-wendelin-serwe, The Unheralded Value of the Multiway Rendezvous: Illustration with the Production Cell Benchmark, Proceedings of the 2nd Workshop on Models for Formal Analysis of Real Systems (MARS'17), vol.244, pp.230-270, 2017.

C. A. Hoare, Communicating Sequential Processes, 1985.

T. Jia and C. Li-&-anping-he, Modeling and Verification of Circuit with Stable-Event, Proceedings of the 2017 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery (CyberC), pp.471-475, 2017.

B. Mark and . Josephs, Receptive Process Theory, vol.29, pp.17-31, 1992.

B. Mark and . Josephs, Gate-level Modelling and Verification of Asynchronous Circuits using CSPM and FDR, Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), pp.83-94, 2007.

K. Hemangee, . Kapoor, B. Mark, and . Josephs, Modelling and Verification of Delay-Insensitive Circuits using CCS and the Concurrency Workbench, Information Processing Letters, vol.89, issue.6, pp.293-296, 2004.

F. Lang, EXP.OPEN 2.0: A Flexible Tool Integrating Partial Order, Compositional, and Onthe-fly Verification Methods, vol.3771, pp.70-88, 2005.
URL : https://hal.archives-ouvertes.fr/inria-00070339

A. J. Martin, Compiling Communicating Processes into Delay-Insensitive VLSI Circuits. Distributed Computing, vol.1, pp.226-234, 1986.

A. J. Martin, 25 Years Ago: The First Asynchronous Microprocessor, Computer Science Technical Reports, vol.001, pp.20140206-111915844, 2014.

D. E. Muller, Theory of Asynchronous Circuits. Research report, vol.66, 1955.

L. A. Plana, P. A. Riocreux, W. J. Bainbridge, A. Bardsley, S. Temple et al., SPA -a secure Amulet core for smartcard applications, Microprocessors and Microsystems, vol.27, issue.9, pp.431-446, 2003.

M. Renaudin and B. Folco, Circuit intégré protégé, Boulahia Boubkar, 2018.

M. Renaudin, B. Folco-&-boulahia, and . Boubkar, Circuit intégré protégé. Fascicule de Brevet Europeen EP 3 276 656 B1, 2019.

A. W. Roscoe, C. A. Hoare-&-richard, and . Bird, The Theory and Practice of Concurrency, 1997.

K. Stevens, J. Aldwinckle, G. Birtwistle, and Y. Liu, Designing Parallel Specifications in CCS, Proceedings of the Canadian Conference on Electrical and Computer Engineering, pp.983-986, 1993.

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