A. Abel and J. Reineke, Measurement-based Modeling of the Cache Replacement Policy, Real-Time and Embedded Technology and Applications Symposium (RTAS), 2013.

A. Cabrera-aldaya, B. B. Brumley, C. P. Sohaib-ul-hassan, N. García, and . Tuveri, Port Contention for Fun and Profit, S&P, 2018.

A. Christensen, Reduce resolution of performance, 2015.

R. Alves, S. Kaxiras, and D. Black-schaffer, Dynamically disabling way-prediction to reduce instruction replay, International Conference on Computer Design (ICCD), 2018.

A. , BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors, 2013.

A. , Software Optimization Guide for AMD Family 15h Processors, 2014.

A. , AMD64 Architecture Programmer's Manual, 2017.

A. , Software Optimization Guide for AMD Family 17h Processors, 2017.

. Amd, Software techniques for managing speculation on AMD processors, 2018.

A. , 2nd Gen AMD EPYC Processors Set New Standard for the Modern Datacenter with Record-Breaking Performance and Significant TCO Savings, 2019.

A. Barresi, K. Razavi, M. Payer, and T. R. Gross, CAIN: Silently Breaking ASLR in the Cloud, WOOT, 2015.

D. J. Bernstein, Cache-Timing Attacks on AES, 2004.

A. Bhattacharyya, A. Sandulescu, M. Neugschwandtner, A. Sorniotti, B. Falsafi et al., SMoTher-Spectre: exploiting speculative execution through port contention, CCS, 2019.

B. Zbarsky, Reduce resolution of performance, 2015.

L. Groot-bruinderink, A. Hülsing, T. Lange, and Y. Yarom, Flush, Gauss, and Reload-a cache attack on the BLISS lattice-based signature scheme, CHES, 2016.

C. Canella, D. Genkin, L. Giner, D. Gruss, M. Lipp et al., Fallout: Leaking Data on Meltdown-resistant CPUs, 2019.

C. Canella, J. V. Bulck, M. Schwarz, M. Lipp, P. Benjamin-von-berg et al., Frank Piessens, Dmitry Evtyushkin, and Daniel Gruss. 2019. A Systematic Evaluation of Transient Execution Attacks and Defenses, USENIX Security Symposium

M. Clark, A new x86 core architecture for the next generation of computing, IEEE Hot Chips Symposium (HCS), 2016.

S. Crane, A. Homescu, S. Brunthaler, P. Larsen, and M. Franz, Thwarting Cache Side-Channel Attacks Through Dynamic Software Diversity, NDSS, 2015.

J. Daemen and V. Rijmen, The design of Rijndael: AES-the advanced encryption standard, 2013.

H. Eijs, PyCryptodome: A self-contained cryptographic library for Python, 2018.

D. Evtyushkin, D. Ponomarev, and N. Abu-ghazaleh, Jump over ASLR: Attacking branch predictors to bypass ASLR, 2016.

W. Shen-gene and S. Nelson, MicroTLB and micro tag for reducing power in a processor, US Patent, vol.7, pp.290-292, 2006.

B. Gras, K. Razavi, H. Bos, and C. Giuffrida, Translation Leak-aside Buffer: Defeating Cache Side-channel Protections with TLB Attacks, USENIX Security Symposium, 2018.

B. Gras, K. Razavi, E. Bosman, H. Bos, and C. Giuffrida, ASLR on the Line: Practical Cache Attacks on the MMU, NDSS, 2017.

W. Gropp, E. Lusk, N. Doss, and A. Skjellum, A highperformance, portable implementation of the MPI message passing interface standard, Parallel computing, 1996.

D. Gruss, M. Lipp, M. Schwarz, R. Fellner, C. Maurice et al., KASLR is Dead: Long Live KASLR, ESSoS, 2017.

D. Gruss, C. Maurice, A. Fogh, M. Lipp, and S. Mangard, Prefetch Side-Channel Attacks: Bypassing SMAP and Kernel ASLR, 2016.

D. Gruss, C. Maurice, and S. Mangard, Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript, DIMVA, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01872588

D. Gruss, C. Maurice, K. Wagner, and S. Mangard, Flush+Flush: A Fast and Stealthy Cache Attack, DIMVA, 2016.

D. Gruss, R. Spreitzer, and S. Mangard, Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches, USENIX Security Symposium, 2015.

. Shay-gueron, Intel Advanced Encryption Standard (Intel AES) Instructions Set -Rev 3, p.1, 2012.

W. Richard and . Hamming, Error detecting and error correcting codes. The Bell system technical journal, 1950.

J. Hruska, AMD Gains Market Share in Desktop and Laptop, 2019.

R. Hund, C. Willems, and T. Holz, Practical Timing Side Channel Attacks against Kernel Space ASLR, S&P, 2013.

K. Inoue, T. Ishihara, and K. Murakami, Way-predicting setassociative cache for high performance and low energy consumption, Symposium on Low Power Electronics and Design, 1999.

G. Irazoqui, T. Eisenbarth, and B. Sunar, S$A: A Shared Cache Attack that Works Across Cores and Defies VM Sandboxing -and its Application to AES, S&P, 2015.

G. Irazoqui, T. Eisenbarth, and B. Sunar, Cross processor cache attacks, AsiaCCS, 2016.

Y. Jang, S. Lee, and T. Kim, Breaking Kernel Address Space Layout Randomization with Intel TSX, CCS, 2016.

E. Richard and . Kessler, The alpha 21264 microprocessor, IEEE Micro, 1999.

P. Kocher, J. Horn, A. Fogh, D. Genkin, D. Gruss et al., Spectre Attacks: Exploiting Speculative Execution, S&P, 2019.

C. Paul and . Kocher, Timing Attacks on Implementations of Diffe-Hellman, RSA, DSS, and Other Systems, CRYPTO, 1996.

R. Könighofer, A Fast and Cache-Timing Resistant Implementation of the AES, 2008.

K. Esmaeil-mohammadian-koruyeh and . Khasawneh, Spectre Returns! Speculation Attacks using the Return Stack Buffer, WOOT, 2018.

M. Krzyzanowski, CryptoSwift: Growing collection of standard and secure cryptographic algorithms implemented in Swift, 2019.

. Linux, Complete virtual memory map with 4-level page tables, 2019.

. Linux, Linux Kernel 5.0 Process (x86, 2019.

M. Lipp, D. Gruss, R. Spreitzer, C. Maurice, and S. Mangard, ARMageddon: Cache Attacks on Mobile Devices, USENIX Security Symposium, 2016.

M. Lipp, M. Schwarz, D. Gruss, T. Prescher, W. Haas et al., Meltdown: Reading Kernel Memory from User Space, USENIX Security Symposium, 2018.

F. Liu, Y. Yarom, Q. Ge, G. Heiser, and R. B. Lee, Last-Level Cache Side-Channel Attacks are Practical, S&P, 2015.

G. Maisuradze and C. Rossow, ret2spec: Speculative Execution Using Return Stack Buffers, CCS, 2018.

C. Maurice, N. L. Scouarnec, C. Neumann, O. Heen, and A. Francillon, Reverse Engineering Intel Complex Addressing Using Performance Counters, RAID, 2015.

C. Maurice, M. Weber, M. Schwarz, L. Giner, D. Gruss et al., Hello from the Other Side: SSH over Robust Cache Covert Channels in the Cloud, NDSS, 2017.

A. Moghimi, G. Irazoqui, and T. Eisenbarth, CacheZoom: How SGX Amplifies The Power of Cache Attacks, CHES, 2017.

R. Moore, pyaes: Pure-Python implementation of AES block-cipher and common modes of operation, 2017.

L. Mouton, N. Jean-phillippe, G. E. Huot, S. Grandou, and . Brochier, Cache accessing using a micro TAG, US Patent, vol.8, p.55, 2012.

Y. Oren, P. Vasileios, S. Kemerlis, A. Sethumadhavan, and . Keromytis, The Spy in the Sandbox: Practical Cache Attacks in JavaScript and their Implications, CCS, 2015.

A. Dag, A. Osvik, E. Shamir, and . Tromer, Cache Attacks and Countermeasures: the Case of AES, 2006.

C. P. , Cache missing for fun and profit, 2005.

P. Pessl, D. Gruss, C. Maurice, M. Schwarz, and S. Mangard, DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks, USENIX Security Symposium, 2016.

K. Moinuddin and . Qureshi, New attacks and defense for encrypted-address cache, ISCA, 2019.

A. D. Chester-rebeiro, A. S. Selvakumar, and . Devi, Bitslice Implementation of AES, Cryptology and Network Security (CANS), 2006.

T. Ristenpart, E. Tromer, H. Shacham, and S. Savage, Hey, You, Get Off of My Cloud: Exploring Information Leakage in Third-Party Compute Clouds, CCS, 2009.

J. David, G. Sager, and . Hinton, Way-predicting cache memory, US Patent, vol.6, p.55, 2002.

M. Schwarz, C. Canella, L. Giner, and D. Gruss, Store-to-Leak Forwarding: Leaking Data on Meltdown-resistant CPUs, 2019.

M. Schwarz, D. Gruss, S. Weiser, C. Maurice, and S. Mangard, Malware Guard Extension: Using SGX to Conceal Cache Attacks, DIMVA, 2017.

M. Schwarz, M. Lipp, D. Gruss, S. Weiser, C. Maurice et al., KeyDrown: Eliminating Software-Based Keystroke Timing Side-Channel Attacks, NDSS, 2018.
URL : https://hal.archives-ouvertes.fr/hal-01872534

M. Schwarz, M. Lipp, D. Moghimi, J. V. Bulck, J. Stecklina et al., ZombieLoad: Cross-Privilege-Boundary Data Sampling, CCS, 2019.

M. Schwarz, C. Maurice, D. Gruss, and S. Mangard, Fantastic Timers and Where to Find Them: High-Resolution Microarchitectural Attacks in JavaScript, FC, 2017.

M. Schwarz, M. Schwarzl, M. Lipp, and D. Gruss, Net-Spectre: Read Arbitrary Memory over Network, ESORICS, 2019.

M. Seaborn, How physical addresses map to rows and banks in DRAM, 2015.

R. Spreitzer and T. Plos, Cache-Access Pattern Attack on Disaligned AES T-Tables, COSADE, 2013.

J. Takahashi, T. Fukunaga, K. Aoki, and H. Fuji, Highly accurate key extraction method for access-driven cache attacks using correlation coefficient, ACISP, 2013.

J. Van-bulck, M. Minkin, O. Weisse, D. Genkin, B. Kasikci et al., Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution, USENIX Security Symposium, 2018.

A. Stephan-van-schaik, S. Milburn, P. Österlund, G. Frigo, K. Maisuradze et al., RIDL: Rogue In-flight Data Load, S&P, 2019.

. Vmware, Security considerations and disallowing inter-Virtual Machine Transparent Page Sharing, 2018.

M. Werner, T. Unterluggauer, L. Giner, M. Schwarz, D. Gruss et al., ScatterCache: Thwarting Cache Attacks via Cache Set Randomization, USENIX Security Symposium, 2019.

F. Wilhelm, PoC for breaking hypervisor ASLR using branch target buffer collisions, 2016.

H. Wong, Intel Ivy Bridge Cache Replacement Policy, 2013.

C. John and . Wray, An analysis of covert timing channels, Journal of Computer Security, vol.1, pp.219-232, 1992.

M. Yan, R. Sprabery, B. Gopireddy, C. Fletcher, R. Campbell et al., Attack directories, not caches: Side channel attacks in a non-inclusive world, S&P, 2019.

Y. Yarom and K. Falkner, Flush+Reload: a High Resolution, Low Noise, L3 Cache Side-Channel Attack, USENIX Security Symposium, 2014.

X. Zhang, Y. Xiao, and Y. Zhang, Return-oriented flushreload side channels on arm and their implications for android devices, CCS, 2016.

Y. Zhang, A. Juels, M. K. Reiter, and T. Ristenpart, Cross-VM Side Channels and Their Use to Extract Private Keys, CCS, 2012.

Y. Zhang, A. Juels, M. K. Reiter, and T. Ristenpart, Cross-Tenant Side-Channel Attacks in PaaS Clouds, CCS, 2014.