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Distributed-memory multi-GPU block-sparse tensor contraction for electronic structure (revised version)

Abstract : Many domains of scientific simulation (chemistry, condensed matter physics, data science) increasingly eschew dense tensors for block-sparse tensors, sometimes with additional structure (recursive hierarchy, rank sparsity, etc.). Distributed-memory parallel computation with block-sparse tensorial data is paramount to minimize the time-tosolution (e.g., to study dynamical problems or for real-time analysis) and to accommodate problems of realistic size that are too large to fit into the host/device memory of a single node equipped with accelerators. Unfortunately, computation with such irregular data structures is a poor match to the dominant imperative, bulk-synchronous parallel programming model. In this paper, we focus on the critical element of block-sparse tensor algebra, namely binary tensor contraction, and report on an efficient and scalable implementation using the task-focused PaRSEC runtime. High performance of the block-sparse tensor contraction on the Summit supercomputer is demonstrated for synthetic data as well as for real data involved in electronic structure simulations of unprecedented size.
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https://hal.inria.fr/hal-02970659
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Submitted on : Sunday, October 18, 2020 - 9:44:56 PM
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Thomas Herault, Yves Robert, George Bosilca, Robert Harrison, Cannada Lewis, et al.. Distributed-memory multi-GPU block-sparse tensor contraction for electronic structure (revised version). [Research Report] RR-9365, Inria - Research Centre Grenoble – Rhône-Alpes. 2020, pp.34. ⟨hal-02970659⟩

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