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From SSA to Synchronous Concurrency and Back

Hugo Pompougnac 1 Ulysse Beaugnon 2 Albert Cohen 2 Dumitru Potop-Butucaru 1
1 KAIROS - Logical Time for Formal Embedded System Design
Laboratoire I3S - COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués, CRISAM - Inria Sophia Antipolis - Méditerranée
Abstract : We are interested in the programming and compilation of reactive, real-time systems. More specifically, we would like to understand the fundamental principles common to generalpurpose and synchronous languages—used to model reactive control systems—and from this to derive a compilation flow suitable for both high-performance and reactive aspects of a modern control application. To this end, we first identify the key operational mechanisms of synchronous languages that SSA does not cover: synchronization of computations with an external time base, cyclic I/O, and the semantic notion of absent value which allows the natural representation of variables whose initialization does not follow simple structural rules such as control flow dominance. Then, we show how the SSA form in its MLIR implementation can be seamlessly extended to cover these mechanisms, enabling the application of all SSA-based transformations and optimizations. We illustrate this on the representation and compilation of the Lustre dataflow synchronous language. Most notably, in the analysis and compilation of Lustre embedded into MLIR, the initialization-related static analysis and code generation aspects can be fully separated from memory allocation and causality aspects, the latter being covered by the existing dominance-based algorithms of MLIR/SSA, resulting in a high degree of conceptual and code reuse. Our work allows the specification of both computational and control aspects of high-performance real-time applications. It paves the way for the definition of more efficient design and implementation flows where real-time ressource allocation drives parallelization and optimization.
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Submitted on : Monday, December 7, 2020 - 4:21:24 PM
Last modification on : Friday, January 21, 2022 - 3:11:25 AM
Long-term archiving on: : Monday, March 8, 2021 - 7:00:16 PM



  • HAL Id : hal-03043623, version 1



Hugo Pompougnac, Ulysse Beaugnon, Albert Cohen, Dumitru Potop-Butucaru. From SSA to Synchronous Concurrency and Back. [Research Report] RR-9380, INRIA Sophia Antipolis - Méditerranée (France). 2020, pp.23. ⟨hal-03043623⟩



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