Safe Overclocking for CNN Accelerators through Algorithm-Level Error Detection - Archive ouverte HAL Access content directly
Journal Articles IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Year : 2020

Safe Overclocking for CNN Accelerators through Algorithm-Level Error Detection

Abstract

In this article, we propose a technique for improving the efficiency of convolutional neural network hardware accelerators based on timing speculation (overclocking) and fault tolerance. We augment the accelerator with a lightweight error detection mechanism to protect against timing errors in convolution layers, enabling aggressive timing speculation. The error detection mechanism we have developed works at the algorithm-level, utilizing algebraic properties of the computation, allowing the full implementation to be realized using high-level synthesis tools. Our prototype on ZC706 demonstrated up to 60% higher throughput with negligible area overhead for various wordlength implementations.
Fichier principal
Vignette du fichier
FINAL VERSION.pdf (1.16 Mo) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

hal-03094811 , version 1 (23-06-2021)

Identifiers

Cite

Thibaut Marty, Tomofumi Yuki, Steven Derrien. Safe Overclocking for CNN Accelerators through Algorithm-Level Error Detection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39 (12), pp.4777 - 4790. ⟨10.1109/TCAD.2020.2981056⟩. ⟨hal-03094811⟩
68 View
140 Download

Altmetric

Share

Gmail Facebook Twitter LinkedIn More