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Safe Overclocking for CNN Accelerators through Algorithm-Level Error Detection

Abstract : In this article, we propose a technique for improving the efficiency of convolutional neural network hardware accelerators based on timing speculation (overclocking) and fault tolerance. We augment the accelerator with a lightweight error detection mechanism to protect against timing errors in convolution layers, enabling aggressive timing speculation. The error detection mechanism we have developed works at the algorithm-level, utilizing algebraic properties of the computation, allowing the full implementation to be realized using high-level synthesis tools. Our prototype on ZC706 demonstrated up to 60% higher throughput with negligible area overhead for various wordlength implementations.
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https://hal.inria.fr/hal-03094811
Contributor : Steven Derrien Connect in order to contact the contributor
Submitted on : Wednesday, June 23, 2021 - 4:05:06 PM
Last modification on : Thursday, November 4, 2021 - 10:54:02 AM
Long-term archiving on: : Friday, September 24, 2021 - 6:51:57 PM

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Thibaut Marty, Tomofumi Yuki, Steven Derrien. Safe Overclocking for CNN Accelerators through Algorithm-Level Error Detection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2020, 39 (12), pp.4777 - 4790. ⟨10.1109/TCAD.2020.2981056⟩. ⟨hal-03094811⟩

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