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A Case for Speculative Strength Reduction

Arthur Perais 1
1 SLS - System Level Synthesis
TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
Abstract : Most high performance general purpose processors leverage register renaming to implement optimizations such as move elimination or zero-idiom elimination. Those optimizations can be seen as forms of strength reduction whereby a faster but semantically equivalent operation is substituted to a slower operation. In this letter, we argue that other reductions can be performed dynamically if input values of instructions are known in time, i.e.,~prior to renaming. We study the potential for leveraging Value Prediction to achieve that goal and show that in SPEC2k17, an average of 3.3% (up to 6.8%) of the dynamic instructions could dynamically be strength reduced. Our experiments suggest that a state-of-the-art value predictor allows to capture 59.7% of that potential on average (up to 99.6%).
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https://hal.archives-ouvertes.fr/hal-03138881
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Submitted on : Monday, March 8, 2021 - 1:58:20 PM
Last modification on : Thursday, March 11, 2021 - 1:44:34 PM
Long-term archiving on: : Wednesday, June 9, 2021 - 7:04:46 PM

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Arthur Perais. A Case for Speculative Strength Reduction. IEEE Computer Architecture Letters, Institute of Electrical and Electronics Engineers, 2021, 20 (1), pp.22-25. ⟨10.1109/LCA.2020.3048694⟩. ⟨hal-03138881⟩

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