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Conference papers

Using an SMT Solver for Checking the Completeness of FSM-Based Tests

Abstract : Deriving tests with guaranteed fault coverage by FSM-based test methods is rather complex for systems with a large number of states. At the same time, formal verification methods allow to effectively process large transition systems; in particular, SMT solvers are widely used to solve analysis problems for finite transition systems. In this paper, we describe the known necessary and sufficient conditions of completeness of test suites derived by FSM-based test methods via the first-order logic formulas and use an SMT solver in order to check them. In addition, we suggest a new sufficient condition for test suite completeness and check the corresponding first-order logic formula via the SMT solver. The results of computer experiments with randomly generated finite state machines confirm the correctness and efficiency of a proposed approach.
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https://hal.inria.fr/hal-03239812
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Submitted on : Thursday, May 27, 2021 - 4:42:16 PM
Last modification on : Thursday, May 27, 2021 - 4:58:44 PM
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Evgenii Vinarskii, Andrey Laputenko, Nina Yevtushenko. Using an SMT Solver for Checking the Completeness of FSM-Based Tests. 32th IFIP International Conference on Testing Software and Systems (ICTSS), Dec 2020, Naples, Italy. pp.289-295, ⟨10.1007/978-3-030-64881-7_18⟩. ⟨hal-03239812⟩

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