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Scheduling paths leveraging dynamic information in SIMT architectures

Lily Blanleuil 1 Caroline Collange 1 
1 PACAP - Pushing Architecture and Compilation for Application Performance
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Thread divergence optimization in GPU architectures have long been hindered by restrictive control-flow mechanisms based on stacks of execution masks. However, GPU architectures recently began implementing more flexible hardware mechanisms, presumably based on path tables. We leverage this opportunity by proposing a hardware implementation of iteration shifting, a divergence optimization that enables lockstep execution across arbitrary iterations of a loop. Although software implementations of iteration shifting have been previously proposed, implementing this scheduling technique in hardware lets us leverage dynamic information such as divergence patterns and memory stalls. Evaluation using simulation suggest that the expected performance improvements will remain modest or even nonexistent unless the organization of the memory access path is also revisited.
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https://hal.inria.fr/hal-03269966
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Submitted on : Thursday, June 24, 2021 - 2:32:39 PM
Last modification on : Monday, April 4, 2022 - 9:28:24 AM
Long-term archiving on: : Saturday, September 25, 2021 - 6:29:43 PM

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  • HAL Id : hal-03269966, version 1

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Lily Blanleuil, Caroline Collange. Scheduling paths leveraging dynamic information in SIMT architectures. COMPAS 2021 - Conférence francophone d'informatique en Parallélisme, Architecture et Système, Jul 2021, Lyon / Virtual, France. pp.1-6. ⟨hal-03269966⟩

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