Skip to Main content Skip to Navigation
Journal articles

Understanding Cache Compression

Daniel Rodrigues Carvalho 1 André Seznec 1 
1 PACAP - Pushing Architecture and Compilation for Application Performance
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Hardware cache compression derives from software-compression research; yet, its implementation is not a straightforward translation, since it must abide by multiple restrictions to comply with area, power, and latency constraints. This study sheds light on the challenges of adopting compression in cache design—from the shrinking of the data until its physical placement. The goal of this article is not to summarize proposals but to put in evidence the solutions they employ to handle those challenges. An in-depth description of the main characteristics of multiple methods is provided, as well as criteria that can be used as a basis for the assessment of such schemes. It is expected that this article will ease the understanding of decisions to be taken for the design of compressed systems and provide directions for future work.
Document type :
Journal articles
Complete list of metadata

https://hal.inria.fr/hal-03285041
Contributor : Erven Rohou Connect in order to contact the contributor
Submitted on : Monday, October 25, 2021 - 3:15:34 PM
Last modification on : Monday, April 4, 2022 - 9:28:24 AM
Long-term archiving on: : Wednesday, January 26, 2022 - 9:06:23 PM

File

Rodrigues Carvalho-2021-Unders...
Publisher files allowed on an open archive

Identifiers

Citation

Daniel Rodrigues Carvalho, André Seznec. Understanding Cache Compression. ACM Transactions on Architecture and Code Optimization, Association for Computing Machinery, 2021, 18 (3), pp.1-27. ⟨10.1145/3457207⟩. ⟨hal-03285041⟩

Share

Metrics

Record views

64

Files downloads

58