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Conciliating Speed and Efficiency on Cache Compressors

Daniel Rodrigues Carvalho 1 André Seznec 1 
1 PACAP - Pushing Architecture and Compilation for Application Performance
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Cache compression algorithms must abide by hardware constraints; thus, their efficiency ends up being low, and most cache lines end up barely compressed. Moreover, schemes that compress relatively well often decompress slowly, and vice versa. This paper proposes a compression scheme achieving high (good) compaction ratio and fast decompression latency. The key observation is that by further subdividing the chunks of data being compressed one can tailor the algorithms. This concept is orthogonal to most existent compressors, and results in a reduction of their average compressed size. In particular, we leverage this concept to boost a single-cycle-decompression compressor to reach a compressibility level competitive to stateof-the-art proposals. When normalized against the best long decompression latency state-of-the-art compressors, the proposed ideas further enhance the average cache capacity by 2.7% (geometric mean), while featuring short decompression latency.
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https://hal.inria.fr/hal-03354883
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Submitted on : Sunday, September 26, 2021 - 8:41:44 PM
Last modification on : Friday, August 5, 2022 - 2:54:52 PM
Long-term archiving on: : Monday, December 27, 2021 - 6:09:57 PM

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  • HAL Id : hal-03354883, version 1

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Daniel Rodrigues Carvalho, André Seznec. Conciliating Speed and Efficiency on Cache Compressors. ICCD 2021 - 39th IEEE International Conference on Computer Design, Oct 2021, Virtual, United States. pp.1-5. ⟨hal-03354883⟩

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