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Conference Papers Year : 2020

Exploiting Heterogeneous Mobile Architectures Through a Unified Runtime Framework

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Chenying Hsieh
  • Function : Author
  • PersonId : 1120096
Ardalan Amiri Sani
  • Function : Author
  • PersonId : 1120097
Nikil Dutt
  • Function : Author
  • PersonId : 1120098

Abstract

Modern mobile SoCs are typically integrated with multiple heterogeneous hardware accelerators such as GPU and DSP. Resource heavy applications such as object detection and image recognition based on convolutional neural networks are accelerated by offloading these computation-intensive algorithms to the accelerators to meet their stringent performance constraints. Conventionally there are device-specific runtime and programming languages supported for programming each accelerator, and these offloading tasks are typically pre-mapped to a specific compute unit at compile time, missing the opportunity to exploit other underutilized compute resources to gain better performance. To address this shortcoming, we present SURF: a Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile Architectures. SURF supports several heterogeneous parallel programming languages (including OpenMP and OpenCL), and enables dynamic task-mapping to heterogeneous resources based on runtime measurement and prediction. The measurement and monitoring loop enables self-aware adaptation of run-time mapping to exploit the best available resource dynamically. Our SURF framework has been implemented on a Qualcomm Snapdragon 835 development board and evaluated on a mix of image recognition (CNN), image filtering applications and synthetic benchmarks to demonstrate the versatility and efficacy of our unified runtime framework.
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Dates and versions

hal-03476612 , version 1 (13-12-2021)

Licence

Attribution - CC BY 4.0

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Chenying Hsieh, Ardalan Amiri Sani, Nikil Dutt. Exploiting Heterogeneous Mobile Architectures Through a Unified Runtime Framework. 27th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2019, Cusco, Peru. pp.323-344, ⟨10.1007/978-3-030-53273-4_15⟩. ⟨hal-03476612⟩
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