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Conference Papers Year : 2020

An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults

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Abstract

Technology scaling increases the integrated circuits susceptibility to Single Event Effects. As a manner to mitigate soft errors, solutions incur significant performance and area penalties, especially when a design with fault-tolerant structure is overprotected. There are several estimation methods, as Probabilistic Transfer Matrix, Signal Probability Reliability, and SPR Multi-Pass, to evaluate circuit reliability. Theses methods use probabilistic transfer matrices (PTM) of the logic gates as the starting point. Few works explore the accurate generation of these matrices. This chapter briefly reviews the reliability concepts and some circuit estimation methods that explore PTM concept and presents a method to provide gate susceptibility matrices considering faults in the stick diagram level. The proposed method enriches the logic gates probabilistic matrices creation taking into account the characteristics of the logic gates to evaluate gate reliability more precisely. The results present the importance of the proposed approach. They are shown in the mean and standard deviation of the susceptibility calculated. In terms of standard deviation, high values indicate that the cell is highly sensitive to pin assignment. A good pin assignment alternative can result in 40% reduction in susceptibility for the same logic function.
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Dates and versions

hal-03476616 , version 1 (13-12-2021)

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Attribution - CC BY 4.0

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Rafael B. Schvittz, Denis T. Franco, Leomar S. da Rosa, Paulo F. Butzen. An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults. 27th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2019, Cusco, Peru. pp.69-88, ⟨10.1007/978-3-030-53273-4_4⟩. ⟨hal-03476616⟩
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