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Compositional synthesis of latency-insensitive systems from multi-clocked synchronous specifications

Jean-Pierre Talpin 1 Dumitru Potop-Butucaru 2 Julien Ouy 1 Benoit Caillaud 3
1 ESPRESSO - Synchronous programming for the trusted component-based engineering of embedded systems and mission-critical systems
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
3 S4 - System synthesis and supervision, scenarios
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : We consider the problem of synthesizing correct-by-construction globally asynchronous, locally synchronous (GALS) implementations from modular synchronous specifications. This involves the synthesis of asynchronous wrappers that drive the synchronous clocks of the modules and perform input reading in such a fashion as to preserve, in a certain sense, the global properties of the system. Our approach is based on the weakly endochronous synchronous model, which gives criteria guaranteeing the existence of simple and efficient asynchronous wrappers. We focus on the transformation (by means of added signalling) of the synchronous modules of a multiclock synchronous specification into weakly endochronous modules, for which simple and efficient wrappers exist. // Nous considérons le problème de transformer une spécification fonctionnelle synchrone multi-horloge en une mise en oeuvre globallement asynchrone de manière modulaire et correcte par construction. Pour cela, nous élaborons une technique de compilation permettant de transformer une spécification déclarative synchrone en un automate effectuant des opérations atomiques de lecture, de calcul et d'écriture et assurant un invariant global d'insensibilité à la latence tout en préservant les propriétés locales de la spécification initiale.
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https://hal.inria.fr/inria-00000175
Contributor : Anne Jaigu <>
Submitted on : Friday, July 22, 2005 - 9:45:52 AM
Last modification on : Friday, January 8, 2021 - 11:30:02 AM
Long-term archiving on: : Thursday, April 1, 2010 - 10:06:21 PM

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  • HAL Id : inria-00000175, version 1

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Jean-Pierre Talpin, Dumitru Potop-Butucaru, Julien Ouy, Benoit Caillaud. Compositional synthesis of latency-insensitive systems from multi-clocked synchronous specifications. [Research Report] PI 1730, 2005, pp.22. ⟨inria-00000175⟩

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