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FPGA Configuration of Intensive Multimedia Processing Tasks Modeled in UML

Sébastien Le Beux 1 Jean-Luc Dekeyser 1 Philippe Marquet 1
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : Recent research have demonstrate interests in a codesign framework     that allows description refinement at different abstraction level.     We have proposed such a framework that allows SoC resources     allocation for regular and repetitive tasks found in intensive     multimedia applications. Nevertheless, the framework does not directly target     reconfigurable architectures, the difficult job of placing and     routing an application on a FPGA being postponed to a dedicated     tool. In order to limit the number of synthesis on this external     tool, we propose an algorithm that, from a high level description     of an intensive multimedia application, estimates the resource     usages on a given FPGA architecture. This algorithm makes use of a     simple mathematical formalism issued from case study     implementations.
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Submitted on : Friday, May 19, 2006 - 7:30:48 PM
Last modification on : Friday, February 4, 2022 - 3:14:48 AM
Long-term archiving on: : Sunday, April 4, 2010 - 8:37:17 PM


  • HAL Id : inria-00070214, version 1


Sébastien Le Beux, Jean-Luc Dekeyser, Philippe Marquet. FPGA Configuration of Intensive Multimedia Processing Tasks Modeled in UML. [Research Report] RR-5810, INRIA. 2006, pp.13. ⟨inria-00070214⟩



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