[. Bolognesi and E. Brinksma, Introduction to the ISO specification language LOTOS, Computer Networks and ISDN Systems, vol.14, issue.1, pp.25-59, 1988.
DOI : 10.1016/0169-7552(87)90085-7

D. Borrione, M. Boubekeur, L. Mounier, M. Renaudin, and A. Sirianni, Validation of Asynchronous Circuit Specifications Using IF/CADP, Proceedings of the International Conference on Very Large Scale Integration of System-on-Chip VLSI-SoC 2003, pp.86-91, 2003.
DOI : 10.1007/0-387-33403-3_6

URL : https://hal.archives-ouvertes.fr/hal-00107431

E. Beigné, F. Clermidy, P. Vivet, A. Clouard, and M. Renaudin, An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework, 11th IEEE International Symposium on Asynchronous Circuits and Systems, pp.54-63, 2005.
DOI : 10.1109/ASYNC.2005.10

[. Bergamini, N. Descoubes, C. Joubert, and R. Mateescu, BISIMULATOR: A Modular Tool for On-the-Fly Equivalence Checking
DOI : 10.1007/978-3-540-31980-1_42

URL : https://hal.archives-ouvertes.fr/hal-00685325

S. Frank, C. De-boer, and . Palamidessi, A Fully Abstract Model for Concurrent Constraint Programming, Proceedings of the International Joint Conference on Theory and Practice of Software Development TAPSOFT'91 Colloquium on Trees in Algebra and Programming CAAP'91, pp.296-319, 1991.

D. Edwards and A. Bardsley, Balsa: An Asynchronous Hardware Synthesis Language, The Computer Journal, vol.45, issue.1, pp.12-18, 2002.
DOI : 10.1093/comjnl/45.1.12

[. Fokkink, Introduction to Process Algebra. Texts in Theoretical Computer Science, 2000.
DOI : 10.1007/978-3-662-04293-9

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.416.274

H. Garavel, F. Lang, and R. Mateescu, Compiler Construction Using LOTOS NT, Proceedings of the 11th International Conference on Compiler Construction CC 2002, pp.9-13, 2002.
DOI : 10.1007/3-540-45937-5_3

[. Garavel, F. Lang, and R. Mateescu, An Overview of CADP European Association for Software Science and Technology (EASST) Newsletter, pp.13-24, 2001.

H. Garavel and J. Sifakis, Compilation and Verification of LOTOS Specifications, Proceedings of the 10th International Symposium on Protocol Specification, Testing and Verification, pp.379-394, 1990.

H. Garavel and M. Sighireanu, A Graphical Parallel Composition Operator for Process Algebras, Proceedings of the Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols, and Protocol Specification, Testing, and Verification FORTE/PSTV'99, pp.185-202, 1999.
DOI : 10.1007/978-0-387-35578-8_11

H. Garavel and W. Serwe, State Space Reduction for Process Algebra Specifications, Proceedings of the 10th International Conference on Algebraic Methodology and Software Technology AMAST, pp.164-180, 2004.
DOI : 10.1007/978-3-540-27815-3_16

S. Hauck, Asynchronous design methodologies: an overview, Proceedings of the IEEE, vol.83, issue.1, pp.69-93, 1995.
DOI : 10.1109/5.362752

[. Iec, LOTOS ? A Formal Description Technique Based on the Temporal Ordering of Observational Behaviour, International Organization for Standardization ? Information Processing Systems ? Open Systems Interconnection, 1989.

L. W. Joep, . Kessels, M. G. Ad, and . Peeters, The Tangram Framework (Embedded Tutorial): Asynchronous Circuits for Low Power, Proceedings of the Asia and South Pacific Design Automation Conference ASP-DAC 2001, pp.255-260, 2001.

[. Lang, Compositional Verification Using SVL Scripts, Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems TACAS'2002, pp.465-469, 2002.
DOI : 10.1007/3-540-46002-0_33

A. J. Martin, The probe: An addition to communication primitives, Information Processing Letters, vol.20, issue.3, pp.125-130, 1985.
DOI : 10.1016/0020-0190(85)90078-X

A. J. Martin, Compiling communicating processes into delay-insensitive VLSI circuits, Distributed Computing, vol.20, issue.8, pp.226-234, 1986.
DOI : 10.1007/BF01660034

URL : http://authors.library.caltech.edu/26661/2/postscript.pdf

[. Milner, A Calculus of Communicating Systems, Lecture Notes in Computer Science, vol.92, 1980.
DOI : 10.1007/3-540-10235-3

[. Nist, Data Encryption Standard (DES) Federal Information Processing Standards FIPS PUB 46-3, National Institute of Standards and Technology, 1999.

M. Renaudin and A. Yakovlev, From Hardware Processes to Asynchronous Circuits via Petri Nets: an Application to Arbiter Design, Proceedings of the Workshop on Token Based Computing TOBACO'04, 2004.
URL : https://hal.archives-ouvertes.fr/hal-01392589

[. Serwe, On Concurrent Functional-Logic Programming, Thèse de doctorat, 2002.

I. J. Van-glabbeek and W. P. Weijland, Branching-Time and Abstraction in Bisimulation Semantics (extended abstract). CS R8911, Centrum voor Wiskunde en Informatica, Also in proc. IFIP 11th World Computer Congress, 1989.

X. Wang, M. Kwiatkowska, G. Theodoropoulos, and Q. Zhang, Towards a Unifying CSP approach to Hierarchical Verification of Asynchronous Hardware, Electronic Notes in Theoretical Computer Science, vol.128, issue.6
DOI : 10.1016/j.entcs.2005.04.014

I. Unité-de-recherche and . Rhône, Alpes 655, avenue de l'Europe -38334 Montbonnot Saint-Ismier (France) Unité de recherche INRIA Futurs : Parc Club Orsay Université -ZAC des Vignes 4

I. Unité-de-recherche and . Lorraine, Technopôle de Nancy-Brabois -Campus scientifique 615, rue du Jardin Botanique -BP 101 -54602 Villers-l` es-Nancy Cedex (France) Unité de recherche INRIA Rennes : IRISA, Campus universitaire de Beaulieu -35042 Rennes Cedex (France) Unité de recherche INRIA Rocquencourt : Domaine de Voluceau -Rocquencourt -BP 105 -78153 Le Chesnay Cedex (France) Unité de recherche, 2004.

I. Editeur and . De-voluceau-rocquencourt, BP 105 -78153 Le Chesnay Cedex (France) http://www.inria.fr ISSN, pp.249-6399