# Latency-Insensitive Design and Central Repetitive Scheduling

1 AOSTE - Models and methods of analysis and optimization for systems with real-time and embedding constraints
CRISAM - Inria Sophia Antipolis - Méditerranée , Inria Paris-Rocquencourt, Laboratoire I3S - COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués
Abstract : The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the inception of arbitrarily fixed (integer) latencies for data/signals traveling along wires or communication media. Then mechanisms such as shell wrappers and relay-stations are introduced to implement'' the necessary back-pressure congestion control, so that data with shorter travel duration can safely await others when they are to be consumed simultaneously by the same computing element. These mechanisms can themselves be efficiently represented as synchronous components in this global, asynchronously-spirited environment. Despite their efficient form, relay-stations and back-pressure mechanisms add complexity to a system whose behaviour is ultimately very repetitive. Indeed, the ''slowest'' data loops regulate the traffic and organize the traffic to their pace. This specific repetitive scheduling has been extensively studied in the past under the name of Central Repetitive Problem'', and results were established proving that so-called k-periodic optimal solutions could be achieved. But the implementation'' using typical synchronous circuit elements in the LID context was never worked out. We deal with these issues here, using explicit representation of schedules as periodic words on ${0,1}^\star$ borrowed from the recently theory of N-synchronous systems.
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Cited literature [16 references]

https://hal.inria.fr/inria-00071374
Contributor : Rapport de Recherche Inria <>
Submitted on : Tuesday, May 23, 2006 - 4:57:01 PM
Last modification on : Monday, November 5, 2018 - 3:36:03 PM
Long-term archiving on : Sunday, April 4, 2010 - 10:07:44 PM

### Identifiers

• HAL Id : inria-00071374, version 1

### Citation

Julien Boucaron, Jean-Vivien Millo, Robert de Simone. Latency-Insensitive Design and Central Repetitive Scheduling. [Research Report] RR-5894, INRIA. 2006. ⟨inria-00071374⟩

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