Understanding cache attacks

Anne Canteaut 1 Cédric Lauradoux 1 André Seznec 2
1 CODES - Coding and cryptography
Inria Paris-Rocquencourt
2 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : This paper points out that both the micro-architecture of the processor and the cache initial state impact the amount of side-channel information which is provided by analyzing the cache behaviour during a symmetric encryption. Therefore, the vulnerability of a block cipher implementation based on lookup tables highly varies with the encryption context and with the targeted platform. Our results then clarify some simulations reported by Bernstein and show that they can be reproduced only in a very particular context. However, we point out that some AES key bits can be recovered even if all lookup tables lie in the cache before each encryption, i.e., if all cache misses are avoided.
Type de document :
Rapport
[Research Report] RR-5881, INRIA. 2006
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Soumis le : mardi 23 mai 2006 - 17:07:02
Dernière modification le : vendredi 16 novembre 2018 - 01:31:01
Document(s) archivé(s) le : dimanche 4 avril 2010 - 22:09:15

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  • HAL Id : inria-00071387, version 1

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Anne Canteaut, Cédric Lauradoux, André Seznec. Understanding cache attacks. [Research Report] RR-5881, INRIA. 2006. 〈inria-00071387〉

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