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Energy reduction potential of a phase-based cache resizing scheme for embedded systems

Gilles Pokam 1 François Bodin 1
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : Managing the energy-performance tradeoff has become a major challenge on embedded systems. The cache hierarchy is a typical example of such a design target where this tradeoff plays a central role. With the increasing level of integration density, a cache can feature several billions of transistors, consuming a large proportion of the energy. In the same time however, it also allows to considerably improve the performance. Configurable caches are becoming the de-facto solution to deal efficiently with that problem. Such caches are equipped with artifacts that enable one to resize it dynamically. In the context of embedded systems, however, many of these artifacts restrict the configurability at the application level. We propose in this paper to modify the structure of a configurable cache to offer embedded compilers the opportunity to reconfigure it according to a program dynamic phase, rather than on a per-application basis. We show in our experimental results that the proposed scheme has a potential for improving the compiler effectiveness to reduce the energy consumption, while not excessively degrading the performance.
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https://hal.inria.fr/inria-00071548
Contributor : Rapport de Recherche Inria <>
Submitted on : Tuesday, May 23, 2006 - 5:55:07 PM
Last modification on : Thursday, January 7, 2021 - 4:27:51 PM
Long-term archiving on: : Sunday, April 4, 2010 - 10:24:20 PM

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  • HAL Id : inria-00071548, version 1

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Gilles Pokam, François Bodin. Energy reduction potential of a phase-based cache resizing scheme for embedded systems. [Research Report] RR-5036, INRIA. 2003. ⟨inria-00071548⟩

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