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Out-of-order Predicated Execution with Translation Register Buffer

Amaury Darsch 1 André Seznec 1
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : New generation superscalar processors combine predication with large resources. A typical example is the EPIC architecture as defined by the canonical IA64 ISA. Unlike traditional ISAs, these new instruction sets are resistant to an out-of-order execution engine, because of the resource size as well as the complexity of executing predicated instructions. In this paper, we present a novel register management policy that facilitates the out-of-order execution of a fully predicated ISA. For this purpose, a new mechanism, called Translation Register Buffer (TRB) is introduced. A translation register acts as an intermediate register that associates a logical register with a physical register. By providing an indirect access to a logical register, the translation register supports the side effects induced by the cancellation of instructions by predicates. In order to demonstrate the TRB validity, a complete simulation framework that fully supports the IA64 ISA has been designed. This original implementation features an emulator and a cycle accurate 10-stage out-of-order core simulator. Our simulation results indicate that, on average, a 10 be achieved, as compared with the equivalent in-order EPIC architecture.
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Submitted on : Tuesday, May 23, 2006 - 6:00:51 PM
Last modification on : Friday, February 4, 2022 - 3:23:20 AM
Long-term archiving on: : Sunday, April 4, 2010 - 10:25:51 PM


  • HAL Id : inria-00071573, version 1


Amaury Darsch, André Seznec. Out-of-order Predicated Execution with Translation Register Buffer. [Research Report] RR-5011, INRIA. 2003. ⟨inria-00071573⟩



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