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Multiplication-addition modulaire: algorithmes itératifs et implantations sur FPGA

Jean-Luc Beuchat 1
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : This paper describes several improvements of an iterative algorithm for modular multiplication originally proposed by Jeong and Burleson. A first modification of the recurrence relation allows us to implement a fused multiply and add unit. Then, we show how to reduce the circuit area by a factor two when the operator offers the possibility to choose the modulo among a set m_1, m_2,, m_q. A new iterative algorithm making the implementation of modular exponentiation easier is eventually discussed. For 16-bit numbers, our operators perform for instance 6 millions of operations per second on a Virtex-E device while only requiring 17 slices.
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Submitted on : Tuesday, May 23, 2006 - 6:40:21 PM
Last modification on : Friday, February 4, 2022 - 3:18:59 AM
Long-term archiving on: : Sunday, April 4, 2010 - 10:36:04 PM


  • HAL Id : inria-00071745, version 1



Jean-Luc Beuchat. Multiplication-addition modulaire: algorithmes itératifs et implantations sur FPGA. RR-4840, INRIA. 2003. ⟨inria-00071745⟩



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