A. Amar, P. Boulet, and J. Dekeyser, ASSEMBLING DYNAMIC COMPONENTS FOR METACOMPUTING USING CORBA, Parallel Computing, 2001.
DOI : 10.1142/9781860949630_0048
URL : https://hal.archives-ouvertes.fr/inria-00565181

A. Amar, P. Boulet, and J. Dekeyser, Towards distributed process networks with CORBA. Parallel and Distributed Computing Practice on Algorithms, 2003. Special Issue on Parallel and Distributed Computing Practice on Algorithms
URL : https://hal.archives-ouvertes.fr/inria-00565180

J. T. Buck, Scheduling dynamic dataflow graphs with bounded memory using the token flow model, IEEE International Conference on Acoustics Speech and Signal Processing, 1993.
DOI : 10.1109/ICASSP.1993.319147

E. A. De-kock, G. Essink, W. J. Smits, P. Van-der-wolf, J. Brunel et al., YAPI, Proceedings of the 37th conference on Design automation , DAC '00, 2000.
DOI : 10.1145/337292.337511

K. Erwin-de, Multiprocessor mapping of process networks: A jpeg decoding case study, International Symposium on System Synthesis, 2002.

G. Kahn, The semantics of a simple language for parallel programming, Information Processing 74: Proceedings of the IFIP Congress, pp.471-475, 1974.

G. Kahn and D. B. Macqueen, Coroutines and networks of parallel processes, Information Processing 77 Proc.IFIP Congress, pp.993-998, 1977.
URL : https://hal.archives-ouvertes.fr/inria-00306565

E. A. Lee, Overview of the Ptolemy Project, 2001.

T. M. Parks, Bounded Scheduling of Process Networks, 1995.

M. Thomas, D. Parks, and . Roberts, Distributed process networks in java, International Workshop on Java for Parallel and Distributed Computing, 2003.

J. Soula, P. Marquet, J. Dekeyser, and A. Demeure, Compilation Principle of a Specification Language Dedicated to Signal Processing, Sixth International Conference on Parallel Computing Technologies, PaCT 2001, pp.358-370, 2001.
DOI : 10.1007/3-540-44743-1_36

D. Webb, A. Wendelborn, and K. Maciunas, Process networks as a highlevel notation for metacomputing, Workshop on Java for Parallel and Distributed Computing (IPPS), 1999.

D. Webb, A. Wendelborn, and J. Ere, A study of computational reconfiguration in a process network, IDEA7, 2000.

. Unité-de-recherche-inria-futurs-domaine-de-voluceau-rocquencourt-bp, Technopôle de Nancy-Brabois -Campus scientifique 615, rue du Jardin Botanique -BP 101 -54602 Villers-lès-Nancy Cedex (France) Unité de recherche INRIA Rennes : IRISA, Campus universitaire de Beaulieu -35042 Rennes Cedex (France) Unité de recherche INRIA Rhône-Alpes : 655, avenue de l'Europe -38330 Montbonnot-St, ) Unité de recherche INRIA Rocquencourt : Domaine de Voluceau -Rocquencourt -BP 105 -78153 Le Chesnay Cedex (France) Unité de recherche INRIA Sophia Antipolis : 2004, route des Lucioles -BP 93 -06902 Sophia Antipolis Cedex, pp.105-78153

I. De-voluceau-rocquencourt, BP 105 -78153 Le Chesnay Cedex (France) http://www.inria.fr ISSN, pp.249-6399